[U-Boot-Users] Bug in AT91RM9200.h
Steven Scholz
steven.scholz at imc-berlin.de
Mon Oct 10 14:33:38 CEST 2005
Ladies,
there's another wrong define in AT91RM9200.
According the (my) User Man the RWHOLD field of SMC_CSR0..SMC_CSR7
starts at bit 28. Thus
#define AT91C_SMC2_RWHOLD ((unsigned int) 0x7 << 29) /*
(SMC2) Read and Write Signal Hold Time */
is rubbish!
So please apply this trivial patch instead if my previous one:
* Fix defines AT91C_SMC2_DBW and AT91C_SMC2_RWHOLD in AT91RM9200.h
Patch by Steven Scholz, 10 Oct 2005
(Machine generate header file - ha, ha!)
--
Steven
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