[U-Boot-Users] Running test code from RAM while having GOT po inting to flash

[atul.sabharwal at exgate.tek.com]

The hardware engineer is initializing the DDR memory correctly.  Otherwise
we won't be able to read/write to the memory.

As I understand, the GOT table is used for relocating the exception vectors.
I am most likely crashing while copying the fixups or when doing a cache
flush.

In start.S, if I disable the ICACHE & do not run the cache POST test which
Enables the I-cache and never disables it, I should be fine.  Unless its
some  852T processor cache bug.  We had problem with ICTRL with value of 7.
Value of 3 seems to work better.  Processor is at 50MHz and memory is at
100MHz with TA line based handshake ( so atomic).

--
Atul