[U-Boot-Users] [PATCH] support for mainstone development board
Frank Agius
Frank.Agius at samsys.com
Wed Oct 26 16:23:47 CEST 2005
Attached are files to add support for the Mainstone development board
(PXA270 CPU). This work was based on the Lubbock module.
CHANGELOG:
* Add support for the Mainstone development board
Patch by Frank Agius, 26 Oct 2005
________________________________________
Frank Agius
SAMSys Technologies, Inc.
Index: MAKEALL
===================================================================
RCS file: /cvsroot/u-boot/u-boot/MAKEALL,v
retrieving revision 1.128
diff -p -u -r1.128 MAKEALL
--- MAKEALL 21 Oct 2005 20:39:10 -0000 1.128
+++ MAKEALL 26 Oct 2005 13:57:35 -0000
@@ -202,8 +202,8 @@ LIST_ARM11=" \
LIST_pxa=" \
adsvix cerf250 cradle csb226 \
- innokom lubbock pxa255_idp wepep250 \
- xaeniax xm250 xsengine \
+ innokom lubbock mainstone pxa255_idp \
+ wepep250 xaeniax xm250 xsengine \
"
LIST_ixp="ixdp425"
Index: Makefile
===================================================================
RCS file: /cvsroot/u-boot/u-boot/Makefile,v
retrieving revision 1.212
diff -p -u -r1.212 Makefile
--- Makefile 15 Oct 2005 17:08:09 -0000 1.212
+++ Makefile 26 Oct 2005 13:57:36 -0000
@@ -1601,6 +1601,9 @@ lubbock_config : unconfig
logodl_config : unconfig
@./mkconfig $(@:_config=) arm pxa logodl
+mainstone_config: unconfig
+ @./mkconfig $(@:_config=) arm pxa mainstone
+
pxa255_idp_config: unconfig
@./mkconfig $(@:_config=) arm pxa pxa255_idp
Index: README
===================================================================
RCS file: /cvsroot/u-boot/u-boot/README,v
retrieving revision 1.138
diff -p -u -r1.138 README
--- README 12 Oct 2005 23:47:18 -0000 1.138
+++ README 26 Oct 2005 13:57:37 -0000
@@ -308,9 +308,9 @@ The following options need to be configu
CONFIG_H2_OMAP1610, CONFIG_HHP_CRADLE,
CONFIG_IMPA7,
CONFIG_INNOVATOROMAP1510, CONFIG_INNOVATOROMAP1610,
CONFIG_KB9202,
CONFIG_LART, CONFIG_LPD7A400,
CONFIG_LUBBOCK,
- CONFIG_OSK_OMAP5912, CONFIG_OMAP2420H4,
CONFIG_SHANNON,
- CONFIG_P2_OMAP730, CONFIG_SMDK2400,
CONFIG_SMDK2410,
- CONFIG_TRAB, CONFIG_VCMA9
+ CONFIG_MAINSTONE, CONFIG_OSK_OMAP5912,
CONFIG_OMAP2420H4,
+ CONFIG_SHANNON, CONFIG_P2_OMAP730,
CONFIG_SMDK2400,
+ CONFIG_SMDK2410, CONFIG_TRAB, CONFIG_VCMA9
MicroBlaze based boards:
------------------------
Index: drivers/smc91111.c
===================================================================
RCS file: /cvsroot/u-boot/u-boot/drivers/smc91111.c,v
retrieving revision 1.19
diff -p -u -r1.19 smc91111.c
--- drivers/smc91111.c 22 Nov 2004 22:20:09 -0000 1.19
+++ drivers/smc91111.c 26 Oct 2005 13:57:40 -0000
@@ -495,7 +495,15 @@ static void smc_enable()
SMC_SELECT_BANK( 0 );
/* see the header file for options in TCR/RCR DEFAULT*/
SMC_outw( TCR_DEFAULT, TCR_REG );
+#ifdef CONFIG_SMC_PXA270
+ /* The promiscuous bit set because I could not receive ARP reply
+ * packets from the server when I send a ARP request. It only works
+ * when I set the promiscuous bit
+ */
+ SMC_outw( RCR_DEFAULT | RCR_PRMS, RCR_REG );
+#else
SMC_outw( RCR_DEFAULT, RCR_REG );
+#endif
/* clear MII_DIS */
/* smc_write_phy_register(PHY_CNTL_REG, 0x0000); */
@@ -529,7 +537,6 @@ static void smc_shutdown()
SMC_outb( TCR_CLEAR, TCR_REG );
}
-
/*
. Function: smc_hardware_send_packet(struct net_device * )
. Purpose:
@@ -640,7 +647,7 @@ again:
}
/* we have a packet address, so tell the card to use it */
-#ifndef CONFIG_XAENIAX
+#ifndef SMC_WRITE_32
SMC_outb (packet_no, PN_REG);
#else
/* On Xaeniax board, we can't use SMC_outb here because that way
@@ -654,7 +661,11 @@ again:
printf ("Write data fifo not empty!\n");
/* point to the beginning of the packet */
+#ifndef CONFIG_SMC_PXA270
SMC_outw (PTR_AUTOINC, PTR_REG);
+#else
+ SMC_outl (PTR_AUTOINC <<16, PTR_REG-2);
+#endif
PRINTK3 ("%s: Trying to xmit packet of length %x\n",
SMC_DEV_NAME, length);
@@ -683,7 +694,7 @@ again:
*/
#ifdef USE_32_BIT
SMC_outsl (SMC91111_DATA_REG, buf, length >> 2);
-#ifndef CONFIG_XAENIAX
+#ifndef SMC_WRITE_32
if (length & 0x2)
SMC_outw (*((word *) (buf + (length & 0xFFFFFFFC))),
SMC91111_DATA_REG);
@@ -708,7 +719,7 @@ again:
SMC_outsw (SMC91111_DATA_REG, buf, (length) >> 1);
#endif /* USE_32_BIT */
-#ifndef CONFIG_XAENIAX
+#ifndef CONFIG_SMC_WRITE_32
/* Send the last byte, if there is one. */
if ((length & 1) == 0) {
SMC_outw (0, SMC91111_DATA_REG);
@@ -716,7 +727,6 @@ again:
SMC_outw (buf[length - 1] | 0x2000, SMC91111_DATA_REG);
}
#endif
-
/* and let the chipset deal with it */
SMC_outw (MC_ENQUEUE, MMU_CMD_REG);
@@ -729,7 +739,7 @@ again:
/* release packet */
/* no need to release, MMU does that now */
-#ifdef CONFIG_XAENIAX
+#ifdef SMC_WRITE_32
SMC_outw (MC_FREEPKT, MMU_CMD_REG);
#endif
@@ -743,6 +753,24 @@ again:
return 0;
} else {
+#ifdef USE_32_BIT
+ /* ack. int */
+ status = SMC_inb (SMC91111_INT_REG);
+ if (status & IM_TX_INT )
+ {
+ SMC_outb (IM_TX_INT, SMC91111_INT_REG);
+ }
+ status = SMC_inb (SMC91111_INT_REG);
+ if (status & IM_TX_EMPTY_INT )
+ SMC_outb (IM_TX_EMPTY_INT, SMC91111_INT_REG);
+ PRINTK2 ("%s: Sent packet of length %d, int status=0x%08x
\n", SMC_DEV_NAME, length, status);
+
+ /* release packet */
+ /* auto release now set, no need to release the tx packet
+ * manually
+ SMC_outb (LAN91C96_MMUCR_RELEASE_TX, LAN91C96_MMU);
+ */
+#else
/* ack. int */
SMC_outb (IM_TX_EMPTY_INT, SMC91111_INT_REG);
/* SMC_outb (IM_TX_INT, SMC91111_INT_REG); */
@@ -751,10 +779,10 @@ again:
/* release packet */
/* no need to release, MMU does that now */
-#ifdef CONFIG_XAENIAX
+#ifdef SMC_WRITE_32
SMC_outw (MC_FREEPKT, MMU_CMD_REG);
#endif
-
+#endif
/* wait for MMU getting ready (low) */
while (SMC_inw (MMU_CMD_REG) & MC_BUSY) {
udelay (10);
@@ -766,7 +794,7 @@ again:
}
/* restore previously saved registers */
-#ifndef CONFIG_XAENIAX
+#ifndef SMC_WRITE_32
SMC_outb( saved_pnr, PN_REG );
#else
/* On Xaeniax board, we can't use SMC_outb here because that way
@@ -805,7 +833,13 @@ void smc_destructor()
*/
static int smc_open (bd_t * bd)
{
- int i, err;
+ int err;
+#ifdef CONFIG_SMC_PXA270
+ long addr0_3;
+ word addr4_5;
+#else
+ int i;
+#endif
PRINTK2 ("%s: smc_open\n", SMC_DEV_NAME);
@@ -828,6 +862,18 @@ static int smc_open (bd_t * bd)
memset (bd->bi_enetaddr, 0, 6); /* hack to make error stick!
upper code will abort if not set */
return (-1); /* upper code ignores this, but NOT
bi_enetaddr */
}
+#ifdef CONFIG_SMC_PXA270
+ /* writes must be on a 32 bit boundary. write first 4 bytes of mac
addr,
+ * then the last 2 bytes.
+ */
+ addr0_3 = smc_mac_addr[3]<<24 | smc_mac_addr[2]<<16 |
smc_mac_addr[1] <<8 | smc_mac_addr[0];
+ /* write first 4 bytes. write address should be on a 32 bit boundary
*/
+ SMC_outl (addr0_3, ADDR0_REG);
+ addr4_5 = smc_mac_addr[5]<<8 | smc_mac_addr[4];
+ PRINTK2("writing smc_mac_addr=0x%06x%x\n",addr0_3,addr4_5);
+ /* write last 2 bytes. write address should be on a 32 bit boundary
*/
+ SMC_outw (addr4_5, ADDR0_REG+4);
+#else
#ifdef USE_32_BIT
for (i = 0; i < 6; i += 2) {
word address;
@@ -840,7 +886,7 @@ static int smc_open (bd_t * bd)
for (i = 0; i < 6; i++)
SMC_outb (smc_mac_addr[i], (ADDR0_REG + i));
#endif
-
+#endif /* end CONFIG_SMC_PXA270 */
return 0;
}
@@ -882,7 +928,12 @@ static int smc_rcv()
PRINTK3("%s: smc_rcv\n", SMC_DEV_NAME);
/* start reading from the start of the packet */
+#ifndef CONFIG_SMC_PXA270
SMC_outw( PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG );
+#else
+ SMC_outl ((PTR_READ | PTR_RCV |
+ PTR_AUTOINC)<<16, 4);
+#endif
/* First two words are status and packet_length */
#ifdef USE_32_BIT
@@ -952,7 +1003,7 @@ static int smc_rcv()
udelay(1); /* Wait until not busy */
/* restore saved registers */
-#ifndef CONFIG_XAENIAX
+#ifndef SMC_WRITE_32
SMC_outb( saved_pnr, PN_REG );
#else
/* On Xaeniax board, we can't use SMC_outb here because that way
@@ -1381,7 +1432,11 @@ static void smc_phy_configure ()
/* Configure the Receive/Phy Control register */
SMC_SELECT_BANK (0);
+#ifdef CONFIG_SMC_PXA270
+ SMC_outl (RPC_DEFAULT<<16, RPC_REG-2);
+#else
SMC_outw (RPC_DEFAULT, RPC_REG);
+#endif
/* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */
my_phy_caps = smc_read_phy_register (PHY_STAT_REG);
@@ -1459,7 +1514,11 @@ static void smc_phy_configure ()
}
/* Re-Configure the Receive/Phy Control register */
+#ifdef CONFIG_SMC_PXA270
+ SMC_outl (RPC_DEFAULT<<16, RPC_REG-2);
+#else
SMC_outw (RPC_DEFAULT, RPC_REG);
+#endif
smc_phy_configure_exit: ;
Index: drivers/smc91111.h
===================================================================
RCS file: /cvsroot/u-boot/u-boot/drivers/smc91111.h,v
retrieving revision 1.11
diff -p -u -r1.11 smc91111.h
--- drivers/smc91111.h 2 Nov 2004 13:00:56 -0000 1.11
+++ drivers/smc91111.h 26 Oct 2005 13:57:41 -0000
@@ -74,7 +74,12 @@ typedef unsigned long int dword;
#define SMC_IO_EXTENT 16
-#ifdef CONFIG_PXA250
+/* XANEIAX and other boards can only do 32-bit writes */
+#if defined (CONFIG_XAENIX) || defined (CONFIG_SMC_PXA270)
+#define SMC_WRITE_32
+#endif
+
+#if defined (CONFIG_PXA250) || defined (CONFIG_PXA27X)
#ifdef CONFIG_XSENGINE
#define SMC_inl(r) (*((volatile dword
*)(SMC_BASE_ADDRESS+(r<<1))))
@@ -176,7 +181,7 @@ typedef unsigned long int dword;
}; \
})
-#else /* if not CONFIG_PXA250 */
+#else /* if not (CONFIG_PXA250 || CONFIG_PXA27X) */
#ifndef CONFIG_SMC_USE_IOFUNCS /* these macros don't work on some boards */
/*
@@ -678,8 +683,11 @@ enum {
--------------------------------------------------------------------------*/
/* select a register bank, 0 to 3 */
-
+#ifdef CONFIG_SMC_PXA270
+#define SMC_SELECT_BANK(x) { SMC_outl( (x)<<16, 12 ); }
+#else
#define SMC_SELECT_BANK(x) { SMC_outw( x, BANK_SELECT ); }
+#endif
/* this enables an interrupt in the interrupt mask register */
#define SMC_ENABLE_INT(x) {\
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