[U-Boot-Users] u-boot 834x spd_ram

Aziz Mzili amzili at Ai-Logix.com
Tue Apr 18 17:45:01 CEST 2006

When is mentioned "cs" i meant the DDR bank cs bounds. In cpu/mpc83xx/spd_ram.c.
They are hardcoded to be 2 and 3. Shouldn't this come from the config ? 
cpu/mpc83xx/spd_ram.c  should be a common code for any 83xx based board not only the freescale board which have the DDR module in the back of the board.
-----Original Message-----
From: u-boot-users-admin at lists.sourceforge.net [mailto:u-boot-users-admin at lists.sourceforge.net]On Behalf Of Ben Warren
Sent: Tuesday, April 18, 2006 10:08 AM
To: Jerry Van Baren
Cc: u-boot-users at lists.sourceforge.net
Subject: Re: [U-Boot-Users] u-boot 834x spd_ram


The 83xx chips have a separate memory bus for DDR, with its own chip selects.  For these chips, you do in fact need to use the local bus CS0 for your boot flash/EEPROM.

I can't find anything in the manual that differentiates between the DDR chip selects, so using CS2/3 was probably just a design choice.


On Tue, 2006-04-18 at 10:02 -0400, Jerry Van Baren wrote: 

Aziz Mzili wrote:


> Hi


> I'm wondering why in cpu/83xx/spd_ram.c we expect the DDR ram to be on 

> cs2 and cs3. Is there any issue with it on cs0 and cs1 ?


> thank you


> Aziz Mzili

I'm not a 834x expert, but all my experience is that CS0 is used to boot 

the processor.  If it is DDR RAM rather than flash, someone other than 

the 834x must initialize the DDR RAM and load it with the boot program. 

  That is possible, but very uncommon.



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