[U-Boot-Users] Incorrect exception reporting for PPC405 in Xilinx VirtexII Pro FPGAs?

[Keith J Outwater]

Stefan Roese <sr at denx.de> wrote on 08/31/2006 02:39:17 AM:

> Hi Keith,
> 
> On Wednesday 30 August 2006 20:07, Keith J Outwater wrote:
> > In the function above, the cause of the exception is being inferred 
from
> > the msr, but according to the Xilinx documentation (PowerPC Processor
> > Reference Guide, EDK 6.1, September 2, 2003), the msr does not provide
> > this information.  In fact, it is the ESR (Exception Syndrome 
Register)
> > that indicated the cause of the exception.
> 
> Good catch.
> 
> > I checked, and it does not appear that this register is provided in 
the
> > pt_regs struct.
> >
> > So now to my question:  Am I on the right track here?  Has anyone else
> > looked at this and fixed this code if it is in fact broken?  If it 
needs
> > fixing, can anyone provide some pointers?
> 
> You seem to be right here. So we (you) need to fix this routine to use 
the 
> correct register (ESR) with the correct bits. Best would be, if you 
could 
> provide a patch. A patch against your 3 weeks old U-Boot version is ok, 
since 
> this file didn't change for a quite long time. And please also provide a 

> CHANGELOG entry.

OK. I'll take a crack at fixing it.  It looks like the biggest issue will 
be
how to add the ppc405 specific registers to the pt_regs struct.

I'm also going to add (configurable) support for dumping the error 
information
registers in the Xilinx PLB2OPB bridge.

Keith

> 
> Thanks.
> 
> Best regards,
> Stefan