[U-Boot-Users] [Patch02.2]AS352X:U-Boot1.1.6 patch 1 for AS352X SOC(New)

thomas thomas.luo at ieee.org
Sat Dec 2 15:49:42 CET 2006


From:thomas.luo at ieee.org
U-Boot1.1.6 for AS352X
Port to U-boot to New ARM base SOC AS352X, support NAND flash Boot.
please ref:
http://www.austriamicrosystems.com/03products/products_detail/AS3525/AS3525.htm
Part 2.2:
Br

Signed-off-by: Thomas Luothomas.luo at austriamicrosystems.com

-------------------------------------------------------------------------------
diff -urN u-boot-1.1.6.org/cpu/arm922t/interrupts.c u-boot-1.1.6/cpu/arm922t/interrupts.c
--- u-boot-1.1.6.org/cpu/arm922t/interrupts.c 1970-01-01 08:00:00.000000000 +0800
+++ u-boot-1.1.6/cpu/arm922t/interrupts.c 2006-11-23 17:01:25.000000000 +0800
@@ -0,0 +1,167 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger at sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu at sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj at denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <arm920t.h>
+#include <asm/proc-armv/ptrace.h>
+
+#ifdef CONFIG_USE_IRQ
+/* enable IRQ interrupts */
+void enable_interrupts (void)
+{
+ unsigned long temp;
+ __asm__ __volatile__("mrs %0, cpsr\n"
+        "bic %0, %0, #0x80\n"
+        "msr cpsr_c, %0"
+        : "=r" (temp)
+        :
+        : "memory");
+}
+
+
+/*
+ * disable IRQ/FIQ interrupts
+ * returns true if interrupts had been enabled before we disabled them
+ */
+int disable_interrupts (void)
+{
+ unsigned long old,temp;
+ __asm__ __volatile__("mrs %0, cpsr\n"
+        "orr %1, %0, #0xc0\n"
+        "msr cpsr_c, %1"
+        : "=r" (old), "=r" (temp)
+        :
+        : "memory");
+ return (old & 0x80) == 0;
+}
+#else
+void enable_interrupts (void)
+{
+ return;
+}
+int disable_interrupts (void)
+{
+ return 0;
+}
+#endif
+
+
+void bad_mode (void)
+{
+ panic ("Resetting CPU ...\n");
+ reset_cpu (0);
+}
+
+void show_regs (struct pt_regs *regs)
+{
+ unsigned long flags;
+ const char *processor_modes[] = {
+ "USER_26", "FIQ_26", "IRQ_26", "SVC_26",
+ "UK4_26", "UK5_26", "UK6_26", "UK7_26",
+ "UK8_26", "UK9_26", "UK10_26", "UK11_26",
+ "UK12_26", "UK13_26", "UK14_26", "UK15_26",
+ "USER_32", "FIQ_32", "IRQ_32", "SVC_32",
+ "UK4_32", "UK5_32", "UK6_32", "ABT_32",
+ "UK8_32", "UK9_32", "UK10_32", "UND_32",
+ "UK12_32", "UK13_32", "UK14_32", "SYS_32",
+ };
+
+ flags = condition_codes (regs);
+
+ printf ("pc : [<%08lx>]    lr : [<%08lx>]\n"
+  "sp : %08lx  ip : %08lx  fp : %08lx\n",
+  instruction_pointer (regs),
+  regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
+ printf ("r10: %08lx  r9 : %08lx  r8 : %08lx\n",
+  regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
+ printf ("r7 : %08lx  r6 : %08lx  r5 : %08lx  r4 : %08lx\n",
+  regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
+ printf ("r3 : %08lx  r2 : %08lx  r1 : %08lx  r0 : %08lx\n",
+  regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
+ printf ("Flags: %c%c%c%c",
+  flags & CC_N_BIT ? 'N' : 'n',
+  flags & CC_Z_BIT ? 'Z' : 'z',
+  flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
+ printf ("  IRQs %s  FIQs %s  Mode %s%s\n",
+  interrupts_enabled (regs) ? "on" : "off",
+  fast_interrupts_enabled (regs) ? "on" : "off",
+  processor_modes[processor_mode (regs)],
+  thumb_mode (regs) ? " (T)" : "");
+}
+
+void do_undefined_instruction (struct pt_regs *pt_regs)
+{
+ printf ("undefined instruction\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+void do_software_interrupt (struct pt_regs *pt_regs)
+{
+ printf ("software interrupt\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+void do_prefetch_abort (struct pt_regs *pt_regs)
+{
+ printf ("prefetch abort\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+void do_data_abort (struct pt_regs *pt_regs)
+{
+ printf ("data abort\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+void do_not_used (struct pt_regs *pt_regs)
+{
+ printf ("not used\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+void do_fiq (struct pt_regs *pt_regs)
+{
+ printf ("fast interrupt request\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+void do_irq (struct pt_regs *pt_regs)
+{
+ printf ("interrupt request\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
diff -urN u-boot-1.1.6.org/cpu/arm922t/Makefile u-boot-1.1.6/cpu/arm922t/Makefile
--- u-boot-1.1.6.org/cpu/arm922t/Makefile 1970-01-01 08:00:00.000000000 +0800
+++ u-boot-1.1.6/cpu/arm922t/Makefile 2006-11-02 22:15:02.000000000 +0800
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(CPU).a
+
+START = start.o
+COBJS = cpu.o interrupts.o
+
+SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+START := $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(START) $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff -urN u-boot-1.1.6.org/cpu/arm922t/start.S u-boot-1.1.6/cpu/arm922t/start.S
--- u-boot-1.1.6.org/cpu/arm922t/start.S 1970-01-01 08:00:00.000000000 +0800
+++ u-boot-1.1.6/cpu/arm922t/start.S 2006-11-30 10:25:41.000000000 +0800
@@ -0,0 +1,353 @@
+/*
+ * Copyright (C) 2006 Austriamicrosystems Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+
+
+/*
+ *************************************************************************
+ *
+ * Jump vector table as in table 3.1 in [1]
+ *
+ *************************************************************************
+ */
+
+
+.globl _start
+_start: b       reset
+ ldr pc, _undefined_instruction
+ ldr pc, _software_interrupt
+ ldr pc, _prefetch_abort
+ ldr pc, _data_abort
+ ldr pc, _not_used
+ ldr pc, _irq
+ ldr pc, _fiq
+
+_undefined_instruction: .word undefined_instruction
+_software_interrupt: .word software_interrupt
+_prefetch_abort: .word prefetch_abort
+_data_abort:  .word data_abort
+_not_used:  .word not_used
+_irq:   .word irq
+_fiq:   .word fiq
+
+ .balignl 16,0xdeadbeef
+
+
+/*
+ *************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ * do important init only if we don't start from memory!
+ * relocate armboot to ram
+ * setup stack
+ * jump to second stage
+ *
+ *************************************************************************
+ */
+
+RAM_END:
+ .word 0x50000
+
+.globl _armboot_start
+_armboot_start:
+ .word _start
+
+/*
+ * These are defined in the board-specific linker script.
+ */
+.globl _bss_start
+_bss_start:
+ .word __bss_start
+
+.globl _bss_end
+_bss_end:
+ .word _end
+
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack memory (calculated at run-time) */
+.globl IRQ_STACK_START
+IRQ_STACK_START:
+ .word _end+200
+
+/* IRQ stack memory (calculated at run-time) */
+.globl FIQ_STACK_START
+FIQ_STACK_START:
+ .word _end+400
+#endif
+
+/*
+ * the actual reset code
+ */
+
+reset:
+ /*
+  * set the cpu to SVC32 mode
+  */
+ mrs r0,cpsr
+ bic r0,r0,#0x1f
+ orr r0,r0,#0xd3
+ msr cpsr,r0
+ 
+ /*
+  * we do sys-critical inits only at reboot,
+  * not when booting from ram!
+  */
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+ bl cpu_init_crit
+#endif
+
+ /* Set up the stack          */
+stack_setup:
+ ldr r0, RAM_END  /* upper 128 KiB: relocated uboot   */
+ sub r0, r0, #CFG_MALLOC_LEN /* malloc area                      */
+ sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo                        */
+ sub sp, r0, #12  /* leave 3 words for abort-stack    */
+
+clear_bss:
+ ldr r0, _bss_start  /* find start of bss segment        */
+ ldr r1, _bss_end  /* stop here                        */
+ mov  r2, #0x00000000  /* clear                            */
+
+clbss_l:str r2, [r0]  /* clear loop...                    */
+ add r0, r0, #4
+ cmp r0, r1
+ ble clbss_l
+ ldr r0,RAM_END
+ ldr r1,_bss_end
+ str r0,_armboot_start
+ add r1,r1,r0
+ str r1,_bss_end
+ ldr r1,_bss_start
+ add r1,r1,r0
+ str r1,_bss_start
+ ldr pc,_start_armboot
+
+_start_armboot: .word start_armboot
+
+
+/*
+ *************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *************************************************************************
+ */
+
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+cpu_init_crit:
+  mrc     p15, 0, r0, c1, c0, 0       @ read CP15 register 1 into r0
+        bic     r0, r0, #0x0001             @ clear bit 0 MMU disable
+        bic     r0, r0, #0x0004             @ clear bit 2 D-cache disable
+        bic     r0, r0, #0x1000             @ clear bit 12 I-cache disable
+        bic     r0, r0, #0xc0000000         @ clear bit 30,31 fast bus mode
+        mcr     p15, 0, r0, c1, c0, 0       @ write value back
+
+        @ invalidate all caches to have a clean startup
+        mov     r2, #0
+        mcr     p15, 0, r2, c7, c7, 0       @ Invalidate D- and I-Cache
+        mcr     p15, 0, r2, c8, c7, 0       @ invalidate all TLBs 
+
+
+ /*
+  * before relocating, we have to setup RAM timing
+  * because memory timing is board-dependend, you will
+  * find a lowlevel_init.S in your board directory.
+  */
+ mov ip, lr
+ bl lowlevel_init
+ mov lr, ip
+ mov pc, lr
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+
+/*
+ *************************************************************************
+ *
+ * Interrupt handling
+ *
+ *************************************************************************
+ */
+
+@
+@ IRQ stack frame.
+@
+#define S_FRAME_SIZE 72
+
+#define S_OLD_R0 68
+#define S_PSR  64
+#define S_PC  60
+#define S_LR  56
+#define S_SP  52
+
+#define S_IP  48
+#define S_FP  44
+#define S_R10  40
+#define S_R9  36
+#define S_R8  32
+#define S_R7  28
+#define S_R6  24
+#define S_R5  20
+#define S_R4  16
+#define S_R3  12
+#define S_R2  8
+#define S_R1  4
+#define S_R0  0
+
+#define MODE_SVC 0x13
+#define I_BIT  0x80
+
+/*
+ * use bad_save_user_regs for abort/prefetch/undef/swi ...
+ * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
+ */
+
+ .macro bad_save_user_regs
+ sub sp, sp, #S_FRAME_SIZE
+ stmia sp, {r0 - r12}   @ Calling r0-r12
+ ldr r2, _armboot_start
+ sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
+ sub r2, r2, #(CFG_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
+ ldmia r2, {r2 - r3}   @ get pc, cpsr
+ add r0, sp, #S_FRAME_SIZE  @ restore sp_SVC
+
+ add r5, sp, #S_SP
+ mov r1, lr
+ stmia r5, {r0 - r3}   @ save sp_SVC, lr_SVC, pc, cpsr
+ mov r0, sp
+ .endm
+
+ .macro irq_save_user_regs
+ sub sp, sp, #S_FRAME_SIZE
+ stmia sp, {r0 - r12}   @ Calling r0-r12
+ add     r8, sp, #S_PC
+ stmdb   r8, {sp, lr}^                   @ Calling SP, LR
+ str     lr, [r8, #0]                    @ Save calling PC
+ mrs     r6, spsr
+ str     r6, [r8, #4]                    @ Save CPSR
+ str     r0, [r8, #8]                    @ Save OLD_R0
+ mov r0, sp
+ .endm
+
+ .macro irq_restore_user_regs
+ ldmia sp, {r0 - lr}^   @ Calling r0 - lr
+ mov r0, r0
+ ldr lr, [sp, #S_PC]   @ Get PC
+ add sp, sp, #S_FRAME_SIZE
+ subs pc, lr, #4   @ return & move spsr_svc into cpsr
+ .endm
+
+ .macro get_bad_stack
+ ldr r13, _armboot_start  @ setup our mode stack
+ sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
+ sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
+
+ str lr, [r13]   @ save caller lr / spsr
+ mrs lr, spsr
+ str     lr, [r13, #4]
+
+ mov r13, #MODE_SVC   @ prepare SVC-Mode
+ @ msr spsr_c, r13
+ msr spsr, r13
+ mov lr, pc
+ movs pc, lr
+ .endm
+
+ .macro get_irq_stack   @ setup IRQ stack
+ ldr sp, IRQ_STACK_START
+ .endm
+
+ .macro get_fiq_stack   @ setup FIQ stack
+ ldr sp, FIQ_STACK_START
+ .endm
+
+/*
+ * exception handlers
+ */
+ .align  5
+undefined_instruction:
+ get_bad_stack
+ bad_save_user_regs
+ bl  do_undefined_instruction
+
+ .align 5
+software_interrupt:
+ get_bad_stack
+ bad_save_user_regs
+ bl  do_software_interrupt
+
+ .align 5
+prefetch_abort:
+ get_bad_stack
+ bad_save_user_regs
+ bl  do_prefetch_abort
+
+ .align 5
+data_abort:
+ get_bad_stack
+ bad_save_user_regs
+ bl  do_data_abort
+
+ .align 5
+not_used:
+ get_bad_stack
+ bad_save_user_regs
+ bl  do_not_used
+
+#ifdef CONFIG_USE_IRQ
+
+ .align 5
+irq:
+ get_irq_stack
+ irq_save_user_regs
+ bl  do_irq
+ irq_restore_user_regs
+
+ .align 5
+fiq:
+ get_fiq_stack
+ /* someone ought to write a more effiction fiq_save_user_regs */
+ irq_save_user_regs
+ bl  do_fiq
+ irq_restore_user_regs
+
+#else
+
+ .align 5
+irq:
+ get_bad_stack
+ bad_save_user_regs
+ bl  do_irq
+
+ .align 5
+fiq:
+ get_bad_stack
+ bad_save_user_regs
+ bl  do_fiq
+
+#endif
diff -urN u-boot-1.1.6.org/CREDITS u-boot-1.1.6/CREDITS
--- u-boot-1.1.6.org/CREDITS 2006-12-01 17:49:32.000000000 +0800
+++ u-boot-1.1.6/CREDITS 2006-11-30 10:30:13.000000000 +0800
@@ -465,3 +465,8 @@
 E: james.macaulay at amirix.com
 D: Suppport for Amirix AP1000
 W: www.amirix.com
+
+N: Thomas Luo 
+E: thomas.luo at austriamicrosystems.com
+D: Port to ARM base SOC AS352X.
+W: www.austriamicrosystems.com


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