[U-Boot-Users] [PATCH 6/8] Support Analogue Micro's ASP8347DB board. CONFIG file.
Pantelis Antoniou
pantelis at embeddedalley.com
Sat Dec 2 23:16:34 CET 2006
Add support for Analogue Micro's ASP8347DB board.
The board is originally shipped with RedBoot.
All appropriate settings are migrated to u-boot & the
old kernel booted; a drop in bootloader replacement.
---
Signed-off-by: Pantelis Antoniou <pantelis at embeddedalley.com>
---
include/configs/ASP8347DB.h | 690 +++++++++++++++++++++++++++++++++++++++++++
1 files changed, 690 insertions(+), 0 deletions(-)
diff --git a/include/configs/ASP8347DB.h b/include/configs/ASP8347DB.h
new file mode 100644
index 0000000..83ffb7b
--- /dev/null
+++ b/include/configs/ASP8347DB.h
@@ -0,0 +1,690 @@
+/*
+ * (C) Copyright 2006
+ * Pantelis Antoniou, Embedded Alley pantelis at embeddedalley.com
+ *
+ * Based on TQM834x by
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * ASP8347DB board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define DEBUG
+#undef DEBUG
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300 1 /* E300 Family */
+#define CONFIG_MPC83XX 1 /* MPC83XX family */
+#define CONFIG_MPC834X 1 /* MPC834X specific */
+#define CONFIG_MPC8349 1 /* MPC8349 specific */
+#define CONFIG_ASP8347DB 1 /* ASP8347DB board specific */
+
+/* IMMR Base Addres Register, use Freescale default: 0xff400000 */
+#define CFG_IMMR 0xff000000
+
+/* System clock. Primary input clock when in PCI host mode */
+#define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */
+
+/*
+ * Local Bus LCRR
+ * LCRR: DLL bypass, Clock divider is 8
+ *
+ * for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
+ *
+ * External Local Bus rate is
+ * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
+ */
+#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_8)
+
+/* board pre init: do not call, nothing to do */
+#undef CONFIG_BOARD_EARLY_INIT_F
+
+/* detect the number of flash banks */
+#define CONFIG_BOARD_EARLY_INIT_R
+
+/* auto complete please */
+#define CONFIG_AUTO_COMPLETE
+
+/*
+ * DDR Setup
+ */
+#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */
+#define CFG_SDRAM_BASE CFG_DDR_BASE
+#define CFG_SDRAM_SIZE 128
+#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
+#define DDR_CASLAT_25 /* CASLAT set to 2.5 */
+#undef CONFIG_DDR_ECC /* only for ECC DDR module */
+#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */
+
+#define CFG_MEMTEST_START 0x00100000 /* memtest region */
+#define CFG_MEMTEST_END 0x00200000
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CFG_FLASH_CFI /* use the Common Flash Interface */
+#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_BASE 0xf0000000 /* start of FLASH */
+#define CFG_FLASH_SIZE 64 /* FLASH size in MB */
+
+/* buffered writes in the AMD chip set is not supported yet */
+#undef CFG_FLASH_USE_BUFFER_WRITE
+
+/*
+ * FLASH bank number detection
+ */
+
+#define CFG_MAX_FLASH_BANKS 1
+#define CFG_MAX_FLASH_SECT 512 /* max sectors per device */
+
+/* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
+#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA) | \
+ BR_MS_GPCM | BR_PS_16 | BR_V)
+
+/* FLASH timing */
+#define CFG_OR_TIMING_FLASH (OR_GPCM_CSNT | OR_GPCM_BCTLD | \
+ OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | \
+ OR_GPCM_SCY_7 | OR_GPCM_TRLX | \
+ OR_GPCM_EHTR)
+
+#define CFG_PRELIM_OR_AM 0xfc000000 /* OR addr mask: 64MB */
+
+#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+
+#define CFG_LBLAWAR0_PRELIM 0x8000001c /* 32 MB size (2^(size + 1)) */
+#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
+
+#define ASP8347DB_FPGA_BASE 0xf8000000
+
+/* FPGA : 32bit */
+#define CFG_BR1_PRELIM ((ASP8347DB_FPGA_BASE & BR_BA) | \
+ BR_MS_GPCM | BR_PS_32 | BR_V)
+#define CFG_OR1_PRELIM (0xffff0000 | OR_GPCM_ACS_0b11 | \
+ OR_GPCM_SCY_15 | OR_GPCM_TRLX | \
+ OR_GPCM_EHTR)
+#define CFG_LBLAWBAR1_PRELIM ASP8347DB_FPGA_BASE
+#define CFG_LBLAWAR1_PRELIM 0x80000016
+
+/* disable remaining mappings */
+#define CFG_BR2_PRELIM 0x00000000
+#define CFG_OR2_PRELIM 0x00000000
+#define CFG_LBLAWBAR2_PRELIM 0x00000000
+#define CFG_LBLAWAR2_PRELIM 0x00000000
+
+#define CFG_BR3_PRELIM 0x00000000
+#define CFG_OR3_PRELIM 0x00000000
+#define CFG_LBLAWBAR3_PRELIM 0x00000000
+#define CFG_LBLAWAR3_PRELIM 0x00000000
+
+#define CFG_BR4_PRELIM 0x00000000
+#define CFG_OR4_PRELIM 0x00000000
+#define CFG_LBLAWBAR4_PRELIM 0x00000000
+#define CFG_LBLAWAR4_PRELIM 0x00000000
+
+#define CFG_BR5_PRELIM 0x00000000
+#define CFG_OR5_PRELIM 0x00000000
+#define CFG_LBLAWBAR5_PRELIM 0x00000000
+#define CFG_LBLAWAR5_PRELIM 0x00000000
+
+#define CFG_BR6_PRELIM 0x00000000
+#define CFG_OR6_PRELIM 0x00000000
+#define CFG_LBLAWBAR6_PRELIM 0x00000000
+#define CFG_LBLAWAR6_PRELIM 0x00000000
+
+#define CFG_BR7_PRELIM 0x00000000
+#define CFG_OR7_PRELIM 0x00000000
+#define CFG_LBLAWBAR7_PRELIM 0x00000000
+#define CFG_LBLAWAR7_PRELIM 0x00000000
+
+/*
+ * Monitor config
+ */
+#define CFG_MONITOR_BASE TEXT_BASE
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#else
+#undef CFG_RAMBOOT
+#endif
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK 1
+#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
+#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX 1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE 1
+#define CFG_NS16550_CLK get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1 (CFG_IMMR + 0x4500)
+#define CFG_NS16550_COM2 (CFG_IMMR + 0x4600)
+
+/*
+ * I2C
+ */
+#undef CONFIG_HARD_I2C /* I2C with hardware support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed: 400KHz */
+#define CFG_I2C_SLAVE 0x7F /* slave address */
+#define CFG_I2C_OFFSET 0x3000
+
+/*
+ * TSEC
+ */
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_MII
+
+#define CFG_TSEC1_OFFSET 0x24000
+#define CFG_TSEC1 (CFG_IMMR + CFG_TSEC1_OFFSET)
+#define CFG_TSEC2_OFFSET 0x25000
+#define CFG_TSEC2 (CFG_IMMR + CFG_TSEC2_OFFSET)
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI
+#endif
+
+#define CONFIG_MPC83XX_TSEC1 1
+#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0"
+#define CONFIG_MPC83XX_TSEC2 1
+#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1"
+#define TSEC1_PHY_ADDR 1
+#define TSEC2_PHY_ADDR 2
+#define TSEC1_PHYIDX 0
+#define TSEC2_PHYIDX 0
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME "TSEC0"
+
+#endif /* CONFIG_TSEC_ENET */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_PCI
+
+#if defined(CONFIG_PCI)
+
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+
+/* PCI1 host bridge */
+#define CFG_PCI1_MEM_BASE 0xc0000000
+#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCI1_IO_BASE 0xe2000000
+#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
+#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
+
+
+#undef CONFIG_EEPRO100
+#define CONFIG_EEPRO100
+#undef CONFIG_TULIP
+
+#if !defined(CONFIG_PCI_PNP)
+ #define PCI_ENET0_IOADDR CFG_PCI1_IO_BASE
+ #define PCI_ENET0_MEMADDR CFG_PCI1_MEM_BASE
+ #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */
+#endif
+
+#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
+
+#endif /* CONFIG_PCI */
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#ifndef CFG_RAMBOOT
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
+#define CFG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
+#define CFG_ENV_SIZE 0x2000
+#else
+#define CFG_NO_FLASH 1 /* Flash is not usable now */
+#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
+#define CFG_ENV_SIZE 0x2000
+#endif
+
+#define CONFIG_LOADS_ECHO 1 /* echo on serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+/* Common commands */
+#define CFG_CMD_ASP8347DB_COMMON CFG_CMD_PING \
+ | CFG_CMD_MII | CFG_CMD_JFFS2
+
+#if defined(CFG_RAMBOOT)
+
+#if defined(CONFIG_PCI)
+#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI \
+ | CFG_CMD_ASP8347DB_COMMON) \
+ & \
+ ~(CFG_CMD_ENV | CFG_CMD_LOADS))
+#else
+#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
+ | CFG_CMD_ASP8347DB_COMMON) \
+ & \
+ ~(CFG_CMD_ENV | CFG_CMD_LOADS))
+#endif
+
+#else /* CFG_RAMBOOT */
+
+#if defined(CONFIG_PCI)
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI \
+ | CFG_CMD_ASP8347DB_COMMON)
+#else
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
+ | CFG_CMD_ASP8347DB_COMMON)
+#endif
+
+#endif /* CFG_RAMBOOT */
+
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_LOAD_ADDR 0x2000000 /* default load address */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer size */
+#define CFG_MAXARGS 16 /* max num of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* boot arg buffer size */
+#define CFG_HZ 1000 /* decrementer freq: 1ms */
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Cache Configuration
+ */
+#define CFG_DCACHE_SIZE 32768
+#define CFG_CACHELINE_SIZE 32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
+#endif
+
+#define CFG_HRCW_LOW ( \
+ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 | \
+ HRCWL_DDR_TO_SCB_CLK_1X1 | \
+ HRCWL_CSB_TO_CLKIN_4X1 | \
+ HRCWL_VCO_BYPASS | \
+ HRCWL_CORE_TO_CSB_1_5X1)
+
+#define CFG_HRCW_HIGH ( \
+ HRCWH_PCI_HOST | \
+ HRCWH_32_BIT_PCI | \
+ HRCWH_PCI1_ARBITER_ENABLE | \
+ HRCWH_PCI2_ARBITER_DISABLE | \
+ HRCWH_CORE_ENABLE | \
+ HRCWH_FROM_0X00000100 | \
+ HRCWH_BOOTSEQ_DISABLE | \
+ HRCWH_SW_WATCHDOG_DISABLE | \
+ HRCWH_ROM_LOC_LOCAL_16BIT | \
+ HRCWH_TSEC1M_IN_GMII | \
+ HRCWH_TSEC2M_IN_GMII)
+
+/* System IO Config */
+#if 0
+#define CFG_SICRH SICRH_TSOBI1
+#define CFG_SICRL SICRL_LDP_A
+#else
+#define CFG_SICRH 0x000000a0
+#define CFG_SICRL 0x80000000
+#endif
+
+/* i-cache and d-cache disabled */
+#define CFG_HID0_INIT 0x000000000
+#define CFG_HID0_FINAL CFG_HID0_INIT
+#define CFG_HID2 HID2_HBE
+
+/* DDR 0 - 128 */
+#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | \
+ BATL_MEMCOHERENCE)
+#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | \
+ BATU_VS | BATU_VP)
+
+/* DCACHE */
+#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | \
+ BATL_MEMCOHERENCE)
+#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | \
+ BATU_VS | BATU_VP)
+
+#define CFG_IBAT2L 0
+#define CFG_IBAT2U 0
+
+/* PCI */
+#ifdef CONFIG_PCI
+#define CFG_IBAT3L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT3U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT4L (CFG_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | \
+ BATL_MEMCOHERENCE)
+#define CFG_IBAT4U (CFG_PCI1_MEM_BASE + 0x10000000 | BATU_BL_256M | \
+ BATU_VS | BATU_VP)
+#define CFG_IBAT5L (CFG_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | \
+ BATL_GUARDEDSTORAGE)
+#define CFG_IBAT5U (CFG_PCI1_IO_BASE + 0x10000000 | BATU_BL_16M | \
+ BATU_VS | BATU_VP)
+#else
+#define CFG_IBAT3L (0)
+#define CFG_IBAT3U (0)
+#define CFG_IBAT4L (0)
+#define CFG_IBAT4U (0)
+#define CFG_IBAT5L (0)
+#define CFG_IBAT5U (0)
+#endif
+
+/* IMMR */
+#define CFG_IBAT6L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | \
+ BATL_GUARDEDSTORAGE)
+#define CFG_IBAT6U (CFG_IMMR | BATU_BL_1M | BATU_VS | BATU_VP)
+
+/* FLASH */
+#define CFG_IBAT7L (CFG_FLASH_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | \
+ BATL_GUARDEDSTORAGE)
+#define CFG_IBAT7U (CFG_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CFG_DBAT0L CFG_IBAT0L
+#define CFG_DBAT0U CFG_IBAT0U
+#define CFG_DBAT1L CFG_IBAT1L
+#define CFG_DBAT1U CFG_IBAT1U
+#define CFG_DBAT2L CFG_IBAT2L
+#define CFG_DBAT2U CFG_IBAT2U
+#define CFG_DBAT3L CFG_IBAT3L
+#define CFG_DBAT3U CFG_IBAT3U
+#define CFG_DBAT4L CFG_IBAT4L
+#define CFG_DBAT4U CFG_IBAT4U
+#define CFG_DBAT5L CFG_IBAT5L
+#define CFG_DBAT5U CFG_IBAT5U
+#define CFG_DBAT6L CFG_IBAT6L
+#define CFG_DBAT6U CFG_IBAT6U
+#define CFG_DBAT7L CFG_IBAT7L
+#define CFG_DBAT7U CFG_IBAT7U
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_ETHADDR D2:DA:5E:44:BC:29
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR 1E:F3:40:21:92:53
+#endif
+
+#define CONFIG_IPADDR 192.168.1.249
+
+#define CONFIG_HOSTNAME asp8347db
+#define CONFIG_ROOTPATH /exports/asp8347db-root
+#define CONFIG_BOOTFILE uImage-rattler
+
+#define CONFIG_SERVERIP 192.168.1.10
+#define CONFIG_GATEWAYIP 192.168.1.1
+#define CONFIG_NETMASK 255.255.255.0
+
+#define CONFIG_LOADADDR 200000 /* default for tftp and bootm */
+
+#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE 38400
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "hostname=asp8347db\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm ${kernel_addr}\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
+ "bootm\0" \
+ "rootpath=/exports/asp8347db-root\0" \
+ "bootfile=uImage-rattler\0" \
+ "kernel_addr=80060000\0" \
+ "ramdisk_addr=80160000\0" \
+ "load=tftp 100000 /tftpboot/asp8347db/u-boot.bin\0" \
+ "update=protect off 80000000 8003ffff; " \
+ "era 80000000 8003ffff; cp.b 100000 80000000 40000\0" \
+ "upd=run load;run update\0" \
+ ""
+
+#define CONFIG_BOOTCOMMAND "run flash_self"
+
+/*
+ * JFFS2 partitions
+ */
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=ASP8347DB"
+
+/* default mtd partition table */
+#define MTDPARTS_DEFAULT "mtdparts=ASP8347DB:" \
+ "256k(u-boot),64k(env),64k(env2)," \
+ "64k(ASP8347DB.FPGA)," \
+ "4m(jffs2),1m(Linux)," \
+ "27136k(spare)," \
+ "64k(RedBoot);"\
+/*
+ * Lattice FPGA configuration support
+ */
+#define CONFIG_FPGA_COUNT 1
+#define CONFIG_FPGA CFG_LATTICE_EC
+#define CFG_FPGA_PROG_FEEDBACK
+
+/*
+ * Enable the call to misc_init_r() for miscellaneous platform
+ * dependent initialization.
+ */
+#define CONFIG_MISC_INIT_R
+
+/*
+ * Enable call to last_stage_init()
+ */
+#define CONFIG_LAST_STAGE_INIT
+
+/*
+ * RedBoot support (this is conditional to CFG_CMD_FLASH)
+ */
+#define CONFIG_REDBOOT 1
+#define CONFIG_REDBOOT_FLASH_SCRIPT_SIZE 512
+#define CONFIG_REDBOOT_FLASH_CONFIG_SIZE 65536
+
+#ifndef __ASSEMBLY__
+
+/* Damn RedBoot has a totally different bd_t */
+typedef struct redboot_bd_info {
+ unsigned int bi_tag; /* Should be 0x42444944 "BDID" */
+ unsigned int bi_size; /* Size of this structure */
+ unsigned int bi_revision; /* revision of this structure */
+ unsigned int bi_bdate; /* bootstrap date, i.e. 0x19971106 */
+ unsigned int bi_memstart; /* Memory start address */
+ unsigned int bi_memsize; /* Memory (end) size in bytes */
+ unsigned int bi_intfreq; /* Internal Freq, in Hz */
+ unsigned int bi_busfreq; /* Bus Freq, in Hz */
+ unsigned int bi_cpmfreq; /* CPM Freq, in Hz */
+ unsigned int bi_brgfreq; /* BRG Freq, in Hz */
+ unsigned int bi_vco; /* VCO Out from PLL */
+ unsigned int bi_pci_freq; /* PCI Freq, in Hz */
+ unsigned int bi_baudrate; /* Default console baud rate */
+ unsigned int bi_immr; /* IMMR when called from boot rom */
+ unsigned char bi_enetaddr[6];
+ unsigned int bi_flashbase; /* Physical address of FLASH memory */
+ unsigned int bi_flashsize; /* Length of FLASH memory */
+ int bi_flashwidth; /* Width (8,16,32,64) */
+ unsigned char *bi_cmdline; /* Pointer to command line */
+ unsigned char bi_esa[3][6]; /* Ethernet station addresses */
+ unsigned int bi_ramdisk_begin;
+ unsigned int bi_ramdisk_end;
+ struct { /* info about [main] video screen */
+ short x_res; /* Horizontal resolution in pixels */
+ short y_res; /* Vertical resolution in pixels */
+ short bpp; /* Bits/pixel */
+ short mode; /* Type of pixels (packed, indexed) */
+ unsigned long fb; /* frame buffer (pixel) memory */
+ } bi_video;
+ void (*bi_cputc)(char); /* Write a character */
+ char (*bi_cgetc)(void); /* Read a character */
+ int (*bi_ctstc)(void); /* Test for input */
+} redboot_bd_t;
+
+#endif
+
+#define CONFIG_REDBOOT_BD_T_SIZE sizeof(redboot_bd_t)
+
+/*
+ * Status LEDs
+ */
+#define CONFIG_STATUS_LED 1 /* Status LED enabled */
+#define CONFIG_BOARD_SPECIFIC_LED /* board has board specific leds */
+
+#define STATUS_LED_BIT LED1
+
+#define STATUS_LED_PERIOD (CFG_HZ / 2)
+#define STATUS_LED_STATE STATUS_LED_BLINKING
+
+#define STATUS_LED_ACTIVE 1 /* LED on for bit == 0 */
+#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
+
+#ifndef __ASSEMBLY__
+
+/* LEDs */
+
+/* led_id_t is unsigned int mask */
+typedef unsigned int led_id_t;
+
+#define __led_toggle(_msk) \
+ do { \
+ ((volatile immap_t *)CFG_IMMR)->pgio[0].dat ^= (_msk); \
+ } while(0)
+
+#define __led_set(_msk, _st) \
+ do { \
+ if ((_st)) \
+ ((volatile immap_t *)CFG_IMMR)->pgio[0].dat |= \
+ (_msk); \
+ else \
+ ((volatile immap_t *)CFG_IMMR)->pgio[0].dat &= \
+ ~(_msk); \
+ } while(0)
+
+#define __led_init(msk, st) __led_set(msk, st)
+
+#endif
+
+/*
+ * GPIOS
+ */
+
+/* easy powerpc bit defines */
+#define _B(x) (1 << (31 - (x)))
+
+/* GPIO1 */
+#define ECP_TMS _B(2) /* FPGA programming */
+#define ECP_TCK _B(3)
+#define ECP_TDI _B(4)
+#define ECP_TDO _B(5)
+#define FPGA_RST _B(6) /* FPGA reset */
+#define USB0_RST _B(7) /* USB0 reset */
+#define USB1_RST _B(8) /* USB1 reset */
+#define LED1 _B(9)
+#define LED2 _B(10)
+#define LED3 _B(11)
+#define LED4 _B(12)
+#define LED_ALL (LED1 | LED2 | LED3 /* | LED4 */ )
+
+/* GPIO2 */
+#define PHY1_RST _B(13) /* PHY1 reset */
+#define PHY2_RST _B(14) /* PHY2 reset */
+#define ETH_RST _B(19) /* Ethernet global reset */
+#define ETH_EN _B(18) /* Ethernet global enable */
+
+#endif /* __CONFIG_H */
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