[U-Boot-Users] Please pull u-boot.git 'mpc83xx' branch
Kumar Gala
galak at kernel.crashing.org
Mon Dec 4 21:32:32 CET 2006
Please pull from 'mpc83xx' branch of
git://git.kernel.org/pub/scm/boot/u-boot/galak/u-boot.git
to receive the following updates:
cpu/mpc83xx/cpu.c | 2 -
cpu/mpc83xx/cpu_init.c | 12 +++----
cpu/mpc83xx/speed.c | 12 +++----
doc/README.mpc83xxads | 2 -
include/asm-ppc/global_data.h | 4 +-
include/asm-ppc/immap_83xx.h | 66 +++++++++++++++++++++---------------------
include/configs/MPC8349EMDS.h | 1
include/configs/MPC8349ITX.h | 1
include/configs/TQM834x.h | 1
include/mpc83xx.h | 10 +++---
10 files changed, 54 insertions(+), 57 deletions(-)
commit cd6447cfd69ace6fc748ff1964d42107bc93beab
Author: Kumar Gala <galak at kernel.crashing.org>
Date: Mon Dec 4 12:42:06 2006 -0600
Fix config of Arbiter, System Priority, and Clock Mode on MPC83xx
The config value for:
* CFG_ACR_PIPE_DEP
* CFG_ACR_RPTCNT
* CFG_SPCR_TSEC1EP
* CFG_SPCR_TSEC2EP
* CFG_SCCR_TSEC1CM
* CFG_SCCR_TSEC2CM
Wasn't not being used when setting the appropriate register
Signed-off-by: Kumar Gala <galak at kernel.crashing.org>
commit 2b0c21e7a44172084a1194897693977d01083e3e
Author: Kumar Gala <galak at kernel.crashing.org>
Date: Mon Dec 4 12:41:37 2006 -0600
Remove CONFIG_MPC8349 and use CONFIG_MPC834X instead
CONFIG_MPC8349 is redudant with CONFIG_MPC834X. Additionally
CONFIG_MPC834X truly states the class of processors the code
is applicable for.
Signed-off-by: Kumar Gala <galak at kernel.crashing.org>
diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c
index 1b51078..7efe7c5 100644
--- a/cpu/mpc83xx/cpu.c
+++ b/cpu/mpc83xx/cpu.c
@@ -97,7 +97,7 @@ int checkcpu(void)
return -1; /* Not sure what this is */
}
-#if defined(CONFIG_MPC8349)
+#if defined(CONFIG_MPC834X)
printf("Rev: %02x at %s MHz\n", (spridr & 0x0000FFFF)>>4 |(spridr & 0x0000000F), strmhz(buf, clock));
#else
printf("Rev: %02x at %s MHz\n", spridr & 0x0000FFFF, strmhz(buf, clock));
diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c
index e5725fb..442937c 100644
--- a/cpu/mpc83xx/cpu_init.c
+++ b/cpu/mpc83xx/cpu_init.c
@@ -69,31 +69,31 @@ void cpu_init_f (volatile immap_t * im)
#ifdef CFG_ACR_PIPE_DEP
/* Arbiter pipeline depth */
- im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | (3 << ACR_PIPE_DEP_SHIFT);
+ im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | (CFG_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
#endif
#ifdef CFG_SPCR_TSEC1EP
/* TSEC1 Emergency priority */
- im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) | (3 << SPCR_TSEC1EP_SHIFT);
+ im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) | (CFG_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT);
#endif
#ifdef CFG_SPCR_TSEC2EP
/* TSEC2 Emergency priority */
- im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) | (3 << SPCR_TSEC2EP_SHIFT);
+ im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) | (CFG_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT);
#endif
#ifdef CFG_SCCR_TSEC1CM
/* TSEC1 clock mode */
- im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) | (1 << SCCR_TSEC1CM_SHIFT);
+ im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) | (CFG_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT);
#endif
#ifdef CFG_SCCR_TSEC2CM
/* TSEC2 & I2C1 clock mode */
- im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) | (1 << SCCR_TSEC2CM_SHIFT);
+ im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) | (CFG_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT);
#endif
#ifdef CFG_ACR_RPTCNT
/* Arbiter repeat count */
- im->arbiter.acr = ((im->arbiter.acr & ~(ACR_RPTCNT)) | (3 << ACR_RPTCNT_SHIFT));
+ im->arbiter.acr = ((im->arbiter.acr & ~(ACR_RPTCNT)) | (CFG_ACR_RPTCNT << ACR_RPTCNT_SHIFT));
#endif
/* RSR - Reset Status Register - clear all status (4.6.1.3) */
diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c
index 7e53b1e..d0fe34a 100644
--- a/cpu/mpc83xx/speed.c
+++ b/cpu/mpc83xx/speed.c
@@ -99,7 +99,7 @@ int get_clocks(void)
u32 lcrr;
u32 csb_clk;
-#if defined(CONFIG_MPC8349)
+#if defined(CONFIG_MPC834X)
u32 tsec1_clk;
u32 tsec2_clk;
u32 usbmph_clk;
@@ -144,7 +144,7 @@ #endif
sccr = im->clk.sccr;
-#if defined(CONFIG_MPC8349)
+#if defined(CONFIG_MPC834X)
switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
case 0:
tsec1_clk = 0;
@@ -249,7 +249,7 @@ #endif
/* unkown SCCR_ENCCM value */
return -6;
}
-#if defined(CONFIG_MPC8349) || defined(CONFIG_MPC8360)
+#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC8360)
lbiu_clk = csb_clk *
(1 + ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT));
#else
@@ -266,7 +266,7 @@ #endif
/* unknown lcrr */
return -10;
}
-#if defined(CONFIG_MPC8349) || defined(CONFIG_MPC8360)
+#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC8360)
ddr_clk = csb_clk *
(1 + ((im->reset.rcwl & RCWL_DDRCM) >> RCWL_DDRCM_SHIFT));
corepll = (im->reset.rcwl & RCWL_COREPLL) >> RCWL_COREPLL_SHIFT;
@@ -314,7 +314,7 @@ #if defined (CONFIG_MPC8360)
#endif
gd->csb_clk = csb_clk;
-#if defined(CONFIG_MPC8349)
+#if defined(CONFIG_MPC834X)
gd->tsec1_clk = tsec1_clk;
gd->tsec2_clk = tsec2_clk;
gd->usbmph_clk = usbmph_clk;
@@ -364,7 +364,7 @@ #endif
printf(" SEC: %4d MHz\n", gd->enc_clk / 1000000);
printf(" I2C1: %4d MHz\n", gd->i2c1_clk / 1000000);
printf(" I2C2: %4d MHz\n", gd->i2c2_clk / 1000000);
-#if defined(CONFIG_MPC8349)
+#if defined(CONFIG_MPC834X)
printf(" TSEC1: %4d MHz\n", gd->tsec1_clk / 1000000);
printf(" TSEC2: %4d MHz\n", gd->tsec2_clk / 1000000);
printf(" USB MPH: %4d MHz\n", gd->usbmph_clk / 1000000);
diff --git a/doc/README.mpc83xxads b/doc/README.mpc83xxads
index d456103..f5ba6a7 100644
--- a/doc/README.mpc83xxads
+++ b/doc/README.mpc83xxads
@@ -49,7 +49,7 @@ Freescale MPC83xx ADS Boards
include/configs/MPC8349ADS.h
CONFIG_MPC83xx MPC83xx family
- CONFIG_MPC8349 MPC8349 specific
+ CONFIG_MPC834X MPC834x specific
CONFIG_MPC8349ADS MPC8349ADS board specific
CONFIG_TSEC_ENET Use on-chip 10/100/1000 ethernet
diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h
index 8bc61b6..c113b7e 100644
--- a/include/asm-ppc/global_data.h
+++ b/include/asm-ppc/global_data.h
@@ -52,12 +52,12 @@ #endif
#if defined(CONFIG_MPC83XX)
/* There are other clocks in the MPC83XX */
u32 csb_clk;
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
u32 tsec1_clk;
u32 tsec2_clk;
u32 usbmph_clk;
u32 usbdr_clk;
-#endif /* CONFIG_MPC8349 */
+#endif /* CONFIG_MPC834X */
u32 core_clk;
u32 i2c1_clk;
u32 i2c2_clk;
diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h
index 43cde5e..b6f5bc4 100644
--- a/include/asm-ppc/immap_83xx.h
+++ b/include/asm-ppc/immap_83xx.h
@@ -90,7 +90,7 @@ #define SPCR_TBEN 0x00400000 /* E300
#define SPCR_TBEN_SHIFT (31-9)
#define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority. */
#define SPCR_COREPR_SHIFT (31-11)
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
#define SPCR_TSEC1DP 0x00003000 /* TSEC1 data priority. */
#define SPCR_TSEC1DP_SHIFT (31-19)
#define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority. */
@@ -110,7 +110,7 @@ #elif defined (CONFIG_MPC8360)
#define SPCR_RES ~(SPCR_PCIHPE|SPCR_PCIPR|SPCR_OPT|SPCR_TBEN|SPCR_COREPR)
#endif
u32 sicrl; /* System General Purpose Register Low */
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
#define SICRL_LDP_A 0x80000000
#define SICRL_USB1 0x40000000
#define SICRL_USB0 0x20000000
@@ -143,7 +143,7 @@ #define SICRL_RES ~(SICRL_LDP_A | SI
#endif
u32 sicrh; /* System General Purpose Register High */
#define SICRH_DDR 0x80000000
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
#define SICRH_TSEC1_A 0x10000000
#define SICRH_TSEC1_B 0x08000000
#define SICRH_TSEC1_C 0x04000000
@@ -314,7 +314,7 @@ #define SICVR_IVECX 0xfc000000 /* Inter
#define SICVR_IVEC 0x0000007f /* Interrupt vector */
#define SICVR_RES ~(SICVR_IVECX|SICVR_IVEC)
u32 sipnr_h; /* System Internal Interrupt Pending Register - High (SIPNR_H) */
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
#define SIIH_TSEC1TX 0x80000000 /* TSEC1 Tx interrupt */
#define SIIH_TSEC1RX 0x40000000 /* TSEC1 Rx interrupt */
#define SIIH_TSEC1ER 0x20000000 /* TSEC1 Eror interrupt */
@@ -333,7 +333,7 @@ #define SIIH_UART2 0x00000040 /* UART
#define SIIH_SEC 0x00000020 /* SEC interrupt */
#define SIIH_I2C1 0x00000004 /* I2C1 interrupt */
#define SIIH_I2C2 0x00000002 /* I2C2 interrupt */
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
#define SIIH_SPI 0x00000001 /* SPI interrupt */
#define SIIH_RES ~(SIIH_TSEC1TX | SIIH_TSEC1RX | SIIH_TSEC1ER \
| SIIH_TSEC2TX | SIIH_TSEC2RX | SIIH_TSEC2ER \
@@ -349,7 +349,7 @@ #endif
#define SIIL_RTCS 0x80000000 /* RTC SECOND interrupt */
#define SIIL_PIT 0x40000000 /* PIT interrupt */
#define SIIL_PCI1 0x20000000 /* PCI1 interrupt */
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
#define SIIL_PCI2 0x10000000 /* PCI2 interrupt */
#endif
#define SIIL_RTCA 0x08000000 /* RTC ALARM interrupt */
@@ -358,7 +358,7 @@ #define SIIL_SBA 0x02000000 /* System
#define SIIL_DMA 0x01000000 /* DMA interrupt */
#define SIIL_GTM4 0x00800000 /* GTM4 interrupt */
#define SIIL_GTM8 0x00400000 /* GTM8 interrupt */
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
#define SIIL_GPIO1 0x00200000 /* GPIO1 interrupt */
#define SIIL_GPIO2 0x00100000 /* GPIO2 interrupt */
#endif
@@ -376,7 +376,7 @@ #define SIIL_GTM7 0x00000400 /* GTM7 i
#define SIIL_GTM1 0x00000020 /* GTM1 interrupt */
#define SIIL_GTM5 0x00000010 /* GTM5 interrupt */
#define SIIL_DPTC 0x00000001 /* DPTC interrupt (!!! Invisible for user !!!) */
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
#define SIIL_RES ~(SIIL_RTCS | SIIL_PIT | SIIL_PCI1 | SIIL_PCI2 \
| SIIL_RTCA | SIIL_MU | SIIL_SBA | SIIL_DMA \
| SIIL_GTM4 | SIIL_GTM8 | SIIL_GPIO1 | SIIL_GPIO2 \
@@ -444,7 +444,7 @@ #define SECNR_RES ~( SECNR_MIXB0T | SECN
#define SERR_IRQ0 0x80000000 /* IRQ0 MCP request */
#define SERR_WDT 0x40000000 /* WDT MCP request */
#define SERR_SBA 0x20000000 /* SBA MCP request */
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
#define SERR_DDR 0x10000000 /* DDR MCP request */
#define SERR_LBC 0x08000000 /* LBC MCP request */
#define SERR_PCI1 0x04000000 /* PCI1 MCP request */
@@ -457,7 +457,7 @@ #define SERR_PCI 0x04000000 /* PCI MCP
#endif
#define SERR_MU 0x01000000 /* MU MCP request */
#define SERR_RNC 0x00010000 /* MU MCP request (!!! Non-visible for users !!!) */
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
#define SERR_RES ~( SERR_IRQ0 | SERR_WDT | SERR_SBA | SERR_DDR \
|SERR_LBC | SERR_PCI1 | SERR_PCI2 | SERR_MU \
|SERR_RNC )
@@ -540,7 +540,7 @@ #define RCWL_LBIUCM 0x80000000 /* LBIUC
#define RCWL_LBIUCM_SHIFT 31
#define RCWL_DDRCM 0x40000000 /* DDRCM */
#define RCWL_DDRCM_SHIFT 30
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
#define RCWL_SVCOD 0x30000000 /* SVCOD */
#endif
#define RCWL_SPMF 0x0f000000 /* SPMF */
@@ -552,7 +552,7 @@ #define RCWL_CEPDF 0x00000020 /* CEPDF
#define RCWL_CEPDF_SHIFT 5
#define RCWL_CEPMF 0x0000001F /* CEPMF */
#define RCWL_CEPMF_SHIFT 0
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
#define RCWL_RES ~(RCWL_LBIUCM|RCWL_DDRCM|RCWL_SVCOD|RCWL_SPMF|RCWL_COREPLL|RCWL_CEVCOD|RCWL_CEPDF|RCWL_CEPMF)
#elif defined (CONFIG_MPC8360)
#define RCWL_RES ~(RCWL_LBIUCM|RCWL_DDRCM|RCWL_SPMF|RCWL_COREPLL|RCWL_CEPDF|RCWL_CEPMF)
@@ -560,7 +560,7 @@ #endif
u32 rcwh; /* RCHL Register */
#define RCWH_PCIHOST 0x80000000 /* PCIHOST */
#define RCWH_PCIHOST_SHIFT 31
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
#define RCWH_PCI64 0x40000000 /* PCI64 */
#define RCWH_PCI1ARB 0x20000000 /* PCI1ARB */
#define RCWH_PCI2ARB 0x10000000 /* PCI2ARB */
@@ -573,7 +573,7 @@ #define RCWH_BMS 0x04000000 /* BMS *
#define RCWH_BOOTSEQ 0x03000000 /* BOOTSEQ */
#define RCWH_SWEN 0x00800000 /* SWEN */
#define RCWH_ROMLOC 0x00700000 /* ROMLOC */
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
#define RCWH_TSEC1M 0x0000c000 /* TSEC1M */
#define RCWH_TSEC2M 0x00003000 /* TSEC2M */
#define RCWH_TPR 0x00000100 /* TPR */
@@ -582,7 +582,7 @@ #define RCWH_SDDRIOE 0x00000010 /* Seco
#endif
#define RCWH_TLE 0x00000008 /* TLE */
#define RCWH_LALE 0x00000004 /* LALE */
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
#define RCWH_RES ~(RCWH_PCIHOST | RCWH_PCI64 | RCWH_PCI1ARB \
| RCWH_PCI2ARB | RCWH_COREDIS | RCWH_BMS \
| RCWH_BOOTSEQ | RCWH_SWEN | RCWH_ROMLOC \
@@ -637,7 +637,7 @@ typedef struct clk83xx {
u32 spmr; /* system PLL mode Register */
#define SPMR_LBIUCM 0x80000000 /* LBIUCM */
#define SPMR_DDRCM 0x40000000 /* DDRCM */
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
#define SPMR_SVCOD 0x30000000 /* SVCOD */
#endif
#define SPMR_SPMF 0x0F000000 /* SPMF */
@@ -647,7 +647,7 @@ #define SPMR_COREPLL 0x007F0000 /* COREP
#define SPMR_CEVCOD 0x000000C0 /* CEVCOD */
#define SPMR_CEPDF 0x00000020 /* CEPDF */
#define SPMR_CEPMF 0x0000001F /* CEPMF */
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
#define SPMR_RES ~(SPMR_LBIUCM | SPMR_DDRCM | SPMR_SVCOD \
| SPMR_SPMF | SPMR_CKID | SPMR_COREPLL \
| SPMR_CEVCOD | SPMR_CEPDF | SPMR_CEPMF)
@@ -660,7 +660,7 @@ #endif
#define OCCR_PCICOE0 0x80000000 /* PCICOE0 */
#define OCCR_PCICOE1 0x40000000 /* PCICOE1 */
#define OCCR_PCICOE2 0x20000000 /* PCICOE2 */
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
#define OCCR_PCICOE3 0x10000000 /* PCICOE3 */
#define OCCR_PCICOE4 0x08000000 /* PCICOE4 */
#define OCCR_PCICOE5 0x04000000 /* PCICOE5 */
@@ -670,7 +670,7 @@ #endif
#define OCCR_PCICD0 0x00800000 /* PCICD0 */
#define OCCR_PCICD1 0x00400000 /* PCICD1 */
#define OCCR_PCICD2 0x00200000 /* PCICD2 */
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
#define OCCR_PCICD3 0x00100000 /* PCICD3 */
#define OCCR_PCICD4 0x00080000 /* PCICD4 */
#define OCCR_PCICD5 0x00040000 /* PCICD5 */
@@ -691,7 +691,7 @@ #define OCCR_RES ~(OCCR_PCICOE0|OCCR_PCI
|OCCR_PCICD0|OCCR_PCICD1|OCCR_PCICD2|OCCR_PCICR )
#endif
u32 sccr; /* system clock control Register */
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
#define SCCR_TSEC1CM 0xc0000000 /* TSEC1CM */
#define SCCR_TSEC1CM_SHIFT 30
#define SCCR_TSEC2CM 0x30000000 /* TSEC2CM */
@@ -699,14 +699,14 @@ #define SCCR_TSEC2CM_SHIFT 28
#endif
#define SCCR_ENCCM 0x03000000 /* ENCCM */
#define SCCR_ENCCM_SHIFT 24
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
#define SCCR_USBMPHCM 0x00c00000 /* USBMPHCM */
#define SCCR_USBMPHCM_SHIFT 22
#define SCCR_USBDRCM 0x00300000 /* USBDRCM */
#define SCCR_USBDRCM_SHIFT 20
#endif
#define SCCR_PCICM 0x00010000 /* PCICM */
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
#define SCCR_RES ~( SCCR_TSEC1CM | SCCR_TSEC2CM | SCCR_ENCCM \
| SCCR_USBMPHCM | SCCR_USBDRCM | SCCR_PCICM)
#endif
@@ -726,7 +726,7 @@ #define PMCCR_DLPEN 0x00000002 /* DDR SD
#if defined (CONFIG_MPC8360)
#define PMCCR_SDLPEN 0x00000004 /* Secondary DDR SDRAM Low Power Enable */
#define PMCCR_RES ~(PMCCR_SLPEN | PMCCR_DLPEN | PMCCR_SDLPEN)
-#elif defined (CONFIG_MPC8349)
+#elif defined (CONFIG_MPC834X)
#define PMCCR_RES ~(PMCCR_SLPEN | PMCCR_DLPEN)
#endif
u32 pmcer; /* PMC Event Register */
@@ -738,7 +738,7 @@ #define PMCMR_RES ~(PMCMR_PMCIE)
u8 res0[0xF4];
} pmc83xx_t;
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
/*
* general purpose I/O module
*/
@@ -1173,7 +1173,7 @@ #define LCRR_CLKDIV_SHIFT 0
u8 res8[0xF00];
} lbus83xx_t;
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
/*
* Serial Peripheral Interface
*/
@@ -1403,18 +1403,18 @@ #define EATCR_ES_MASK 0x000f0000 /* err
#define EATCR_ES_EM 0x00000000 /* external master */
#define EATCR_ES_DMA 0x00050000
#define EATCR_CMD_MASK 0x0000f000
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
#define EATCR_HBE_MASK 0x00000f00 /* PCI high byte enable */
#endif
#define EATCR_BE_MASK 0x000000f0 /* PCI byte enable */
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
#define EATCR_HPB 0x00000004 /* high parity bit */
#endif
#define EATCR_PB 0x00000002 /* parity bit */
#define EATCR_VI 0x00000001 /* error information valid */
u32 eacr;
u32 eeacr;
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
u32 edlcr;
u32 edhcr;
#elif defined (CONFIG_MPC8360)
@@ -1477,7 +1477,7 @@ #define PIWAR_IWS_1G 0x0000001D
#define PIWAR_IWS_2G 0x0000001E
} pcictrl83xx_t;
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
/*
* USB
*/
@@ -1988,7 +1988,7 @@ typedef struct immap {
reset83xx_t reset; /* Reset Module */
clk83xx_t clk; /* System Clock Module */
pmc83xx_t pmc; /* Power Management Control Module */
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
gpio83xx_t pgio[2]; /* general purpose I/O module */
#elif defined (CONFIG_MPC8360)
qepi83xx_t qepi; /* QE Ports Interrupts Registers */
@@ -1999,7 +1999,7 @@ #if defined (CONFIG_MPC8360)
#endif
u8 DDL_DDR[0x100];
u8 DDL_LBIU[0x100];
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
u8 res1[0xE00];
#elif defined (CONFIG_MPC8360)
u8 res1[0x200];
@@ -2010,7 +2010,7 @@ #endif
fsl_i2c_t i2c[2]; /* I2C Controllers */
u8 res2[0x1300];
duart83xx_t duart[2]; /* DUART */
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
u8 res3[0x900];
lbus83xx_t lbus; /* Local Bus Controller Registers */
u8 res4[0x1000];
@@ -2022,7 +2022,7 @@ #elif defined (CONFIG_MPC8360)
u8 res4[0x2000];
#endif
dma83xx_t dma; /* DMA */
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
pciconf83xx_t pci_conf[2]; /* PCI Software Configuration Registers */
ios83xx_t ios; /* Sequencer */
pcictrl83xx_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 5bed2d0..400583c 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -37,7 +37,6 @@ #undef DEBUG
#define CONFIG_E300 1 /* E300 Family */
#define CONFIG_MPC83XX 1 /* MPC83XX family */
#define CONFIG_MPC834X 1 /* MPC834X family */
-#define CONFIG_MPC8349 1 /* MPC8349 specific */
#define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */
#undef CONFIG_PCI
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index cbdbb29..5e64772 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -62,7 +62,6 @@ #undef DEBUG
* High Level Configuration Options
*/
#define CONFIG_MPC834X /* MPC834x family (8343, 8347, 8349) */
-#define CONFIG_MPC8349 /* MPC8349 specific */
#define CONFIG_PCI
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 728083b..7903a48 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -37,7 +37,6 @@ #undef DEBUG
#define CONFIG_E300 1 /* E300 Family */
#define CONFIG_MPC83XX 1 /* MPC83XX family */
#define CONFIG_MPC834X 1 /* MPC834X specific */
-#define CONFIG_MPC8349 1 /* MPC8349 specific */
#define CONFIG_TQM834X 1 /* TQM834X board specific */
/* IMMR Base Addres Register, use Freescale default: 0xff400000 */
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 03dd0ca..005c043 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -140,7 +140,7 @@ #define BR_ATOM_SHIFT 2
#endif
#define BR_V 0x00000001
#define BR_V_SHIFT 0
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)
#elif defined (CONFIG_MPC8360)
#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_ATOM|BR_V)
@@ -227,7 +227,7 @@ #define OR_SDRAM_EAD_SHIFT 0
#define HRCWH_PCI_AGENT 0x00000000
#define HRCWH_PCI_HOST 0x80000000
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
#define HRCWH_32_BIT_PCI 0x00000000
#define HRCWH_64_BIT_PCI 0x40000000
#endif
@@ -235,7 +235,7 @@ #endif
#define HRCWH_PCI1_ARBITER_DISABLE 0x00000000
#define HRCWH_PCI1_ARBITER_ENABLE 0x20000000
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
#define HRCWH_PCI2_ARBITER_DISABLE 0x00000000
#define HRCWH_PCI2_ARBITER_ENABLE 0x10000000
#elif defined (CONFIG_MPC8360)
@@ -258,14 +258,14 @@ #define HRCWH_SW_WATCHDOG_ENABLE 0x0
#define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000
#define HRCWH_ROM_LOC_PCI1 0x00100000
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
#define HRCWH_ROM_LOC_PCI2 0x00200000
#endif
#define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000
#define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000
#define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000
-#if defined (CONFIG_MPC8349)
+#if defined (CONFIG_MPC834X)
#define HRCWH_TSEC1M_IN_RGMII 0x00000000
#define HRCWH_TSEC1M_IN_RTBI 0x00004000
#define HRCWH_TSEC1M_IN_GMII 0x00008000
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