[U-Boot-Users] MPC8360E & Large DDR Capacities

[Russell McGuire]

Does anybody know if there are any issues with using DDR capacities above
256MB? I am attempting to use a 512MB DIMM at the moment, and am not sure if
I am getting a SDRAM init issue that is causing U-boot to continuously
reset, <Yes I have read the U-boot FAQ on this>, or whether I have hosed
over the BAT setup trying to cache all 512MB.

I see in the code there is a single CONFIG_VERY_BIG_RAM setting, and in the
board.c file that 'may' effect the position of the final stack location.

As well I have a question regarding a MAXIMUM supportable RAM by U-boot.
I.e. could it go as high as 2 GB? And if so, what would the BAT settings
look like. I am assuming that each bat on the E300 core can only map 256MB,
so would it require all 8 BATS just to map the DDR? Or can the BATS just be
enabled for the lower portions, or is there some nifty way to link them to
span higher ranges than 256MB?

As well I have mapped the DDRLAW0 to span a single 512MB range.
Each CS0 and CS1 is mapped to handle 256MB.

See my current BATS below:

My Laws are using 
/* DDR: cache cacheable, first 256MB, should be 0x0000_0000 to 0x0FFF_FFFF*/
#define CFG_IBAT0L	(CFG_DDR_SDRAM_BASE | BATL_PP_10 |
BATL_MEMCOHERENCE)
#define CFG_IBAT0U	(CFG_DDR_SDRAM_BASE | BATU_BL_256M | BATU_VS |
BATU_VP)
#define CFG_DBAT0L	CFG_IBAT0L
#define CFG_DBAT0U	CFG_IBAT0U

/* DDR: cache cacheable, second 256MB, should be 0x1000_0000 to
0x1FFF_FFFF*/
#define CFG_IBAT1L	((CFG_DDR_SDRAM_BASE+0x10000000) | BATL_PP_10 |
BATL_MEMCOHERENCE)
#define CFG_IBAT1U	((CFG_DDR_SDRAM_BASE+0x10000000) | BATU_BL_256M |
BATU_VS | BATU_VP)
#define CFG_DBAT1L	CFG_IBAT1L
#define CFG_DBAT1U	CFG_IBAT1U


-Russ