[U-Boot-Users] u-boot kernel parameters

[Simon Yang]

Hi Travis,

Thanks for your reply. I still have a question, for rgmii mode the bits 11:9
of phy reg 0x17 should be 001 which means the I/O pin operate from 2.5V,
default is 3.3V if the value of bits 11:9 is 000, so whether I should
set reg 0x17 to 1200.

The cpu we use is MPC8349E, I set the reg ECNTRL to 0x00001010 , I can
meature the signals on TSEC1_GTX_CLK, Tx_EN and Tx_D[0:3], the RGMII should
operate on 2.5v but the voltage I meature on Tx_D is 3.3v , so there is a
problem  that the value of reg SICRH(in local memory offset is 0x118) is
always 00000002(GMII mode and RGMII mode), but in the datasheet of MPC8349E
the bits 30 and 31of reg SICRH (TSOBI1 and TSOBI2) controls the output
buffer impedance of the TSEC1and TSEC2 output signals, so I think the value
I get is not what I expected. Cany anybody tell me how the reg SICRH get
this value? Seems SICRH only use in /cpu/mpc83xx/cpu_init.c file. Thanks a
lot!


2006/2/15, Travis B. Sawyer <tsawyer at sandburst.com>:
>
> Simon Yang wrote:
> > Dear All,
> >
> > Now I am working on CIS8201 PHY for RGMII mode, I have modified Reg
> > 23(0x17h) from 0000 to 1300, but CIS8201 doesn't work under RGMII
> > mode, are there other registers I need to set? Please give me your
> > comment. Thanks a lot!
> >
> Simon:
> If you're using the ocotea, phy reg 0x17 should be written with 0x1000
> for rgmii mode, not 0x1300.  0x300 enables clock skewing for boards with
> short etch, like the Sandburst Metrobox and Karef boards.  The ocotea
> has full length etch and doesn't (or rather should not) use clock skewing.
>
>
> Das U-Boot current source should 'just work' on the ocotea board.
>
> (I can't verify the current source as I haven't done a git sync since
> Stefan merged/fixed the 4xx files, too many time constraints here at
> work, so I'm working with an 'older' tree).
>
> -travis
>
>
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