[U-Boot-Users] [DNX#2006100542000034] [PATCH] Fix PCI, USB, bootargs for MPC8349E-mITX

[DENX Support System]

Hello list,

inside the automatic U-Boot patch tracking system a new ticket
[DNX#2006100542000034] was created:

<snip>
> From: Timur Tabi <timur at freescale.com>
> 
> PREREQUISITE PATCHES:
> 
> * This patch can only be applied after the following patches have been
> applied:
> 
>   1) DNX#2006092142000015 "Add support for the MPC8349E-mITX  1/2"
>   2) DNX#2006092142000024 "Add support for the MPC8349E-mITX  2/2"
> 
> CHANGELOG:
> 
> * For the 8349E-mITX, fix some size values in pci_init_board(), enable
>   the clock for the 2nd USB board (Linux kernel will hang otherwise),
>   and fix the CONFIG_BOOTARGS macro.
> 
> Signed-off-by: Timur Tabi <timur at freescale.com>
> ---
>  board/mpc8349itx/pci.c       |   14 +++++++-------
>  include/configs/MPC8349ITX.h |   19 +++++++++++--------
>  2 files changed, 18 insertions(+), 15 deletions(-)
> 
> diff --git a/board/mpc8349itx/pci.c b/board/mpc8349itx/pci.c
> index 22ab736..c90ccc0 100644
> --- a/board/mpc8349itx/pci.c
> +++ b/board/mpc8349itx/pci.c
> @@ -153,7 +153,7 @@ #endif
>  	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
>  
>  	pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
> -	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
> +	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M;
>  
>  	/*
>  	 * Configure PCI Outbound Translation Windows
> @@ -162,17 +162,17 @@ #endif
>  	/* PCI1 mem space - prefetch */
>  	pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
>  	pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
> -	pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | (POCMR_CM_256M &
> POCMR_CM_MASK);
> +	pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | POCMR_CM_256M;
>  
>  	/* PCI1 IO space */
>  	pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
>  	pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
> -	pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M &
> POCMR_CM_MASK);
> +	pci_pot[1].pocmr = POCMR_EN | POCMR_IO | POCMR_CM_16M;
>  
>  	/* PCI1 mmio - non-prefetch mem space */
>  	pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK;
>  	pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK;
> -	pci_pot[2].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK);
> +	pci_pot[2].pocmr = POCMR_EN | POCMR_CM_256M;
>  
>  	/*
>  	 * Configure PCI Inbound Translation Windows
> @@ -259,17 +259,17 @@ #ifdef CONFIG_MPC83XX_PCI2
>  	/* PCI2 mem space - prefetch */
>  	pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
>  	pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
> -	pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN |
> (POCMR_CM_256M & POCMR_CM_MASK);
> +	pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN |
> POCMR_CM_256M;
>  
>  	/* PCI2 IO space */
>  	pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
>  	pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
> -	pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_1M &
> POCMR_CM_MASK);
> +	pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | POCMR_CM_16M;
>  
>  	/* PCI2 mmio - non-prefetch mem space */
>  	pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK;
>  	pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK;
> -	pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | (POCMR_CM_256M &
> POCMR_CM_MASK);
> +	pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_CM_256M;
>  
>  	/*
>  	 * Configure PCI Inbound Translation Windows
> diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
> index aed350f..20f3c6d 100644
> --- a/include/configs/MPC8349ITX.h
> +++ b/include/configs/MPC8349ITX.h
> @@ -604,7 +604,7 @@ #define CFG_ACR_RPTCNT		3	/* Arbiter rep
>  
>  /* System IO Config */
>  #define CFG_SICRH SICRH_TSOBI1	/* Needed for gigabit to work on TSEC 1
> */
> -#define CFG_SICRL SICRL_LDP_A
> +#define CFG_SICRL (SICRL_LDP_A | SICRL_USB1)
>  
>  #define CFG_HID0_INIT 0x000000000
>  
> @@ -701,7 +701,7 @@ #define CONFIG_IPADDR		10.82.19.159
>  #define CONFIG_SERVERIP		10.82.48.106
>  #define CONFIG_GATEWAYIP	10.82.19.254
</snip>

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