[U-Boot-Users] nand flash controller on 440ep/epx

[Jeff Mann]

Stefan:

>Use the least significant 2 bit's in the CFG_NAND_BASE_LIST to select
the CS. 
>In your case this would look like this:

>#define CFG_NAND_BASE_LIST	{ CFG_NAND_BASE + 1, CFG_NAND_BASE + 2 }

>The driver could then configure the correct CS in the new device select
function, and would of course mask the least significant 2 bit's in the
IO_ADDR_W/_R accesses.

>Is this too "hackish"?

That would work. Is simple, and would work for initialization. It would
involve using a proper mask for nand_baseaddr[..] when setting the
location of the nand read/write/control registers to ignore the CS data.


So.....

Nand_init(...) calls nand_init_chip(...) which then calls
board_nand_init(...)
I think the most appropriate place to select the proper Chip select is
in the board_nand_init() function. This function is only passed an
address of the chip nand_chip struct address. So I still think that an
entry in the nand_chip struct should be used for tracking the chip
select to keep the chip select code out of nand.c and keep the code as
simple as possible. 

So, I like the 
#define CFG_NAND_BASE_LIST	{ CFG_NAND_BASE + 1, CFG_NAND_BASE + 2 }

configuration method, but I still think that the struct nand_chip needs
a chip select variable. 

Do we assume the use of the nand flash controller on PPC 440 EP, Epx,
GP, and GPx processors by default (unless still using the legacy drivers
like the bamboo board)?

What do you think?

-Jeff