[U-Boot-Users] [PATCH 2/2] Adding support for KS8993, KS8893, KS8721 and KS8001 for AT91RM9200 based boards
Mirco Fuchs
mircofuchs at web.de
Wed Oct 11 14:22:11 CEST 2006
Hi,
this patch includes the header files for Micrel's switches KS8893 and KS8993
and for Micrel's PHYs KS8721 and KS8001.
Best Regards
Mirco
Signed-off-by: Mirco Fuchs mircofuchs at web.de
diff --git a/include/ks8893.h b/include/ks8893.h
new file mode 100644
index 0000000..a0a01e7
--- /dev/null
+++ b/include/ks8893.h
@@ -0,0 +1,145 @@
+/*
+ * Micrel KS8893 Ethernet Switch
+ *
+ * (C) Copyright 2006
+ * Authors :
+ * Udo Jakobza (jakobza at ftz-leipzig.de)
+ * Mirco Fuchs (fuchs at ftz-leipzig.de)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __KS8893_H_
+#define __KS8893_H_
+
+/* Micrel Ethernet Switch KS8893 Global Registers (Extended via SMI) */
+#define KS8893_CPID0_REG 0 /* Chip ID0 register */
+#define KS8893_CPID1_REG 1 /* Chip ID1 / Start Switch register
*/
+#define KS8893_GLB_CTL4_REG 6
+
+/* Micrel Ethernet Switch KS8893 Port1 Registers (Extended via SMI) */
+#define KS8893_PORT1_CTL0_REG 16
+#define KS8893_PORT1_CTL1_REG 17
+#define KS8893_PORT1_CTL2_REG 18
+#define KS8893_PORT1_CTL3_REG 19
+#define KS8893_PORT1_CTL4_REG 20
+#define KS8893_PORT1_CTL5_REG 21
+#define KS8893_PORT1_CTL6_REG 22
+#define KS8893_PORT1_CTL7_REG 23
+#define KS8893_PORT1_CTL8_REG 24
+#define KS8893_PORT1_CTL9_REG 25
+#define KS8893_PORT1_CTL10_REG 26
+#define KS8893_PORT1_CTL11_REG 27
+#define KS8893_PORT1_CTL12_REG 28
+#define KS8893_PORT1_CTL13_REG 29
+#define KS8893_PORT1_STAT0_REG 30
+#define KS8893_PORT1_STAT1_REG 31
+
+/* Micrel Ethernet Switch KS8893 Port2 Registers (Extended via SMI) */
+#define KS8893_PORT2_CTL0_REG 32
+#define KS8893_PORT2_CTL1_REG 33
+#define KS8893_PORT2_CTL2_REG 34
+#define KS8893_PORT2_CTL3_REG 35
+#define KS8893_PORT2_CTL4_REG 36
+#define KS8893_PORT2_CTL5_REG 37
+#define KS8893_PORT2_CTL6_REG 38
+#define KS8893_PORT2_CTL7_REG 39
+#define KS8893_PORT2_CTL8_REG 40
+#define KS8893_PORT2_CTL9_REG 41
+#define KS8893_PORT2_CTL10_REG 42
+#define KS8893_PORT2_CTL11_REG 43
+#define KS8893_PORT2_CTL12_REG 44
+#define KS8893_PORT2_CTL13_REG 45
+#define KS8893_PORT2_STAT0_REG 46
+#define KS8893_PORT2_STAT1_REG 47
+
+/* Micrel Ethernet Switch KS8893 Port2 Registers (Extended via SMI) */
+#define KS8893_PORT3_CTL0_REG 48
+#define KS8893_PORT3_CTL1_REG 49
+#define KS8893_PORT3_CTL2_REG 50
+#define KS8893_PORT3_CTL3_REG 51
+#define KS8893_PORT3_CTL4_REG 52
+#define KS8893_PORT3_CTL5_REG 53
+#define KS8893_PORT3_CTL6_REG 54
+#define KS8893_PORT3_CTL7_REG 55
+#define KS8893_PORT3_CTL8_REG 56
+#define KS8893_PORT3_CTL9_REG 57
+#define KS8893_PORT3_CTL10_REG 58
+#define KS8893_PORT3_CTL11_REG 59
+#define KS8893_PORT3_STAT1_REG 63
+
+/*--definitions: KS8893_CPID0_REG */
+#define KS8893_CHIPID0 0x88 /* bits 0-1 from Chip Id */
+
+/*--definitions: KS8893_CPID0_REG */
+#define KS8893_CHIPID1 0x2 << 4 /* bits 2-3 from Chip Id */
+#define KS8893_REVID 0x0 << 3 /* not defined */
+#define KS8893_START_SW 0x1 << 0 /* start chip */
+
+/*--definitions: KS8893_GLB_CTL4_REG */
+#define KS8893_MII_HD 1 << 6 /* MII interface is HD when set */
+#define KS8893_MII_FLWCTL_EN 1 << 5 /* MII i. flow ctl. enable when set
*/
+#define KS8893_MII_10BT 1 << 4 /* MII i. is in 10 Mbps mode
when set */
+#define KS8893_NULL_VID 1 << 3 /* replace NULL VID with port
VID */
+#define KS8893_BCAST_SP_10_8 0 /* bit 10:8 of broadcast strom prot.
*/
+
+/*--definitions: KS8893_PORT_CTL12_REG */
+#define KS8893_ANEG_EN 1 << 7 /* if set, auto-negotiation is on */
+#define KS8893_FCE_SPEED 1 << 6 /* select speed if AN is disabled */
+#define KS8893_FCE_DUPLEX 1 << 5 /* select duplex if AN is disabled */
+#define KS8893_ADV_FLWCTL 1 << 4 /* flow control capability (for AN)
*/
+#define KS8893_ADV_100_FD 1 << 3 /* 100 MBit full duplex cap. (for AN)
*/
+#define KS8893_ADV_100_HD 1 << 2 /* 100 MBit half duplex cap. (for AN)
*/
+#define KS8893_ADV_10_FD 1 << 1 /* 10 MBit full duplex cap. (for AN)
*/
+#define KS8893_ADV_10_HD 1 << 0 /* 100 MBit full duplex cap. (for AN)
*/
+
+/*--definitions: KS8893_PORT_CTL13_REG */
+#define KS8893_LED_OFF 1 << 7 /* turns off all port's LEDs */
+#define KS8893_TX_DIS 1 << 6 /* disables transmitter when set */
+#define KS8893_RESTART_AN 1 << 5 /* restart auto-negotiation */
+#define KS8893_FAR_END_FLT_DIS 1 << 4 /* disables far end fault when set */
+#define KS8893_PWR_DOWN 1 << 3 /* power down when set */
+#define KS8893_AUTO_MDIX_DIS 1 << 2 /* disables auto MDI-X function */
+#define KS8893_FCE_MDIX 1 << 1 /* force MDI or MDI-X*/
+#define KS8893_LOOPBACK 1 << 0 /* enable loopback */
+
+/*--definitions: KS8893_PORT_STAT0_REG */
+#define KS8893_MDIX 1 << 7 /* MDI-X is enabled when set */
+#define KS8893_AN_RDY 1 << 6 /* Auto-negotiation ready */
+#define KS8893_LNK_UP 1 << 5 /* Link-Up */
+#define KS8893_PART_FLWCTL 1 << 4 /* partner flow control cabability */
+#define KS8893_PART_100_FD 1 << 3 /* partner 100 MBit full duplex cap.
*/
+#define KS8893_PART_100_HD 1 << 2 /* partner 100 MBit half duplex cap.
*/
+#define KS8893_PART_10_FD 1 << 1 /* partner 10 MBit full duplex cap.
*/
+#define KS8893_PART_10_HD 1 << 0 /* partner 10 MBit half duplex cap.
*/
+
+/*--definitions: KS8893_PORT_STAT1_REG */
+#define KS8893_RX_FLWCTL_EN 1 << 4 /* receive flow control */
+#define KS8893_TX_FLWCTL_EN 1 << 3 /* transmit flow control */
+#define KS8893_LNK_SPEED 1 << 2 /* operation speed (1 = 100 MBit) */
+#define KS8893_LNK_DUPLEX 1 << 1 /* operation duplex (1 = full duplex)
*/
+#define KS8893_FAR_END_FAULT 1 << 0 /* far end fault status (only port 1)
*/
+
+/****************** function prototypes **********************/
+unsigned int ks8893_IsPhyConnected(AT91PS_EMAC p_mac);
+unsigned char ks8893_GetLinkSpeed(AT91PS_EMAC p_mac);
+unsigned char ks8893_AutoNegotiate(AT91PS_EMAC p_mac, int *status);
+unsigned char ks8893_InitPhy(AT91PS_EMAC p_mac);
+
+#endif /* __KS8893_H_ */
diff --git a/include/ks8993.h b/include/ks8993.h
new file mode 100644
index 0000000..613f734
--- /dev/null
+++ b/include/ks8993.h
@@ -0,0 +1,145 @@
+/*
+ * Micrel KS8993 Ethernet Switch
+ *
+ * (C) Copyright 2006
+ * Authors :
+ * Udo Jakobza (jakobza at ftz-leipzig.de)
+ * Mirco Fuchs (fuchs at ftz-leipzig.de)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __KS8993_H_
+#define __KS8993_H_
+
+/* Micrel Ethernet Switch KS8993 Global Registers (Extended via SMI) */
+#define KS8993_CPID0_REG 0 /* Chip ID0 register */
+#define KS8993_CPID1_REG 1 /* Chip ID1 / Start Switch register
*/
+#define KS8993_GLB_CTL4_REG 6
+
+/* Micrel Ethernet Switch KS8993 Port1 Registers (Extended via SMI) */
+#define KS8993_PORT1_CTL0_REG 16
+#define KS8993_PORT1_CTL1_REG 17
+#define KS8993_PORT1_CTL2_REG 18
+#define KS8993_PORT1_CTL3_REG 19
+#define KS8993_PORT1_CTL4_REG 20
+#define KS8993_PORT1_CTL5_REG 21
+#define KS8993_PORT1_CTL6_REG 22
+#define KS8993_PORT1_CTL7_REG 23
+#define KS8993_PORT1_CTL8_REG 24
+#define KS8993_PORT1_CTL9_REG 25
+#define KS8993_PORT1_CTL10_REG 26
+#define KS8993_PORT1_CTL11_REG 27
+#define KS8993_PORT1_CTL12_REG 28
+#define KS8993_PORT1_CTL13_REG 29
+#define KS8993_PORT1_STAT0_REG 30
+#define KS8993_PORT1_STAT1_REG 31
+
+/* Micrel Ethernet Switch KS8993 Port2 Registers (Extended via SMI) */
+#define KS8993_PORT2_CTL0_REG 32
+#define KS8993_PORT2_CTL1_REG 33
+#define KS8993_PORT2_CTL2_REG 34
+#define KS8993_PORT2_CTL3_REG 35
+#define KS8993_PORT2_CTL4_REG 36
+#define KS8993_PORT2_CTL5_REG 37
+#define KS8993_PORT2_CTL6_REG 38
+#define KS8993_PORT2_CTL7_REG 39
+#define KS8993_PORT2_CTL8_REG 40
+#define KS8993_PORT2_CTL9_REG 41
+#define KS8993_PORT2_CTL10_REG 42
+#define KS8993_PORT2_CTL11_REG 43
+#define KS8993_PORT2_CTL12_REG 44
+#define KS8993_PORT2_CTL13_REG 45
+#define KS8993_PORT2_STAT0_REG 46
+#define KS8993_PORT2_STAT1_REG 47
+
+/* Micrel Ethernet Switch KS8993 Port2 Registers (Extended via SMI) */
+#define KS8993_PORT3_CTL0_REG 48
+#define KS8993_PORT3_CTL1_REG 49
+#define KS8993_PORT3_CTL2_REG 50
+#define KS8993_PORT3_CTL3_REG 51
+#define KS8993_PORT3_CTL4_REG 52
+#define KS8993_PORT3_CTL5_REG 53
+#define KS8993_PORT3_CTL6_REG 54
+#define KS8993_PORT3_CTL7_REG 55
+#define KS8993_PORT3_CTL8_REG 56
+#define KS8993_PORT3_CTL9_REG 57
+#define KS8993_PORT3_CTL10_REG 58
+#define KS8993_PORT3_CTL11_REG 59
+#define KS8993_PORT3_STAT1_REG 63
+
+/*--definitions: KS8993_CPID0_REG */
+#define KS8993_CHIPID0 0x93 /* bits 0-1 from Chip Id */
+
+/*--definitions: KS8993_CPID0_REG */
+#define KS8993_CHIPID1 0x0 << 4 /* bits 2-3 from Chip Id */
+#define KS8993_REVID 0x0 << 3 /* not defined */
+#define KS8993_START_SW 0x1 << 0 /* start chip */
+
+/*--definitions: KS8993_GLB_CTL4_REG */
+#define KS8993_MII_HD 1 << 6 /* MII interface is HD when set */
+#define KS8993_MII_FLWCTL_EN 1 << 5 /* MII i. flow ctl. enable when set
*/
+#define KS8993_MII_10BT 1 << 4 /* MII i. is in 10 Mbps mode
when set */
+#define KS8993_NULL_VID 1 << 3 /* replace NULL VID with port
VID */
+#define KS8993_BCAST_SP_10_8 0 /* bit 10:8 of broadcast strom prot.
*/
+
+/*--definitions: KS8993_PORT_CTL12_REG */
+#define KS8993_ANEG_EN 1 << 7 /* if set, auto-negotiation is on */
+#define KS8993_FCE_SPEED 1 << 6 /* select speed if AN is disabled */
+#define KS8993_FCE_DUPLEX 1 << 5 /* select duplex if AN is disabled */
+#define KS8993_ADV_FLWCTL 1 << 4 /* flow control capability (for AN)
*/
+#define KS8993_ADV_100_FD 1 << 3 /* 100 MBit full duplex cap. (for AN)
*/
+#define KS8993_ADV_100_HD 1 << 2 /* 100 MBit half duplex cap. (for AN)
*/
+#define KS8993_ADV_10_FD 1 << 1 /* 10 MBit full duplex cap. (for AN)
*/
+#define KS8993_ADV_10_HD 1 << 0 /* 100 MBit full duplex cap. (for AN)
*/
+
+/*--definitions: KS8993_PORT_CTL13_REG */
+#define KS8993_LED_OFF 1 << 7 /* turns off all port's LEDs */
+#define KS8993_TX_DIS 1 << 6 /* disables transmitter when set */
+#define KS8993_RESTART_AN 1 << 5 /* restart auto-negotiation */
+#define KS8993_FAR_END_FLT_DIS 1 << 4 /* disables far end fault when set */
+#define KS8993_PWR_DOWN 1 << 3 /* power down when set */
+#define KS8993_AUTO_MDIX_DIS 1 << 2 /* disables auto MDI-X function */
+#define KS8993_FCE_MDIX 1 << 1 /* force MDI or MDI-X*/
+#define KS8993_LOOPBACK 1 << 0 /* enable loopback */
+
+/*--definitions: KS8993_PORT_STAT0_REG */
+#define KS8993_MDIX 1 << 7 /* MDI-X is enabled when set */
+#define KS8993_AN_RDY 1 << 6 /* Auto-negotiation ready */
+#define KS8993_LNK_UP 1 << 5 /* Link-Up */
+#define KS8993_PART_FLWCTL 1 << 4 /* partner flow control cabability */
+#define KS8993_PART_100_FD 1 << 3 /* partner 100 MBit full duplex cap.
*/
+#define KS8993_PART_100_HD 1 << 2 /* partner 100 MBit half duplex cap.
*/
+#define KS8993_PART_10_FD 1 << 1 /* partner 10 MBit full duplex cap.
*/
+#define KS8993_PART_10_HD 1 << 0 /* partner 10 MBit half duplex cap.
*/
+
+/*--definitions: KS8993_PORT_STAT1_REG */
+#define KS8993_RX_FLWCTL_EN 1 << 4 /* receive flow control */
+#define KS8993_TX_FLWCTL_EN 1 << 3 /* transmit flow control */
+#define KS8993_LNK_SPEED 1 << 2 /* operation speed (1 = 100 MBit) */
+#define KS8993_LNK_DUPLEX 1 << 1 /* operation duplex (1 = full duplex)
*/
+#define KS8993_FAR_END_FAULT 1 << 0 /* far end fault status (only port 1)
*/
+
+/****************** function prototypes **********************/
+unsigned int ks8993_IsPhyConnected(AT91PS_EMAC p_mac);
+unsigned char ks8993_GetLinkSpeed(AT91PS_EMAC p_mac);
+unsigned char ks8993_AutoNegotiate(AT91PS_EMAC p_mac, int *status);
+unsigned char ks8993_InitPhy(AT91PS_EMAC p_mac);
+
+#endif /* __KS8993_H_ */
diff --git a/include/ks8xx1.h b/include/ks8xx1.h
new file mode 100644
index 0000000..9ae057f
--- /dev/null
+++ b/include/ks8xx1.h
@@ -0,0 +1,115 @@
+/*
+ * Micrel KS8xx1 Ethernet PHY
+ *
+ * (C) Copyright 2006
+ * Authors :
+ * Udo Jakobza (jakobza at ftz-leipzig.de)
+ * Mirco Fuchs (fuchs at ftz-leipzig.de)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Micrel PHYSICAL LAYER TRANSCEIVER KS8xx1 */
+
+#define KS8xx1_BCR 0 /* Basic Control Register */
+#define KS8xx1_BSR 1 /* Basic Status Register */
+#define KS8xx1_PHYID1 2 /* PHY Idendifier Register 1 */
+#define KS8xx1_PHYID2 3 /* PHY Idendifier Register 2 */
+#define KS8xx1_ANAR 4 /* Auto_Negotiation Advertisement Register
*/
+#define KS8xx1_ANLPAR 5 /* Auto_N. Link Partner Ability Register */
+#define KS8xx1_ANER 6 /* Auto-N. Expansion Register */
+#define KS8xx1_ANNPR 7 /* Auto-N. Next Page Register */
+#define KS8xx1_LPNPA 8 /* Link Partner Next Page Ability */
+#define KS8xx1_RXERCR 21 /* RXER Counter Register */
+#define KS8xx1_ICSR 27 /* Interrupt Control/Status Register */
+#define KS8xx1_TXPCR 31 /* 100BASE-TX PHY Control Register */
+
+/* --Bit definitions: KS8xx1_BCR */
+#define KS8xx1_RESET (1 << 15)
+#define KS8xx1_LOOPBACK (1 << 14)
+#define KS8xx1_SPEED_SELECT (1 << 13)
+#define KS8xx1_AUTONEG (1 << 12)
+#define KS8xx1_POWER_DOWN (1 << 11)
+#define KS8xx1_ISOLATE (1 << 10)
+#define KS8xx1_RESTART_AUTONEG (1 << 9)
+#define KS8xx1_DUPLEX_MODE (1 << 8)
+#define KS8xx1_COLLISION_TEST (1 << 7)
+#define KS8xx1_DIS_TX (1 << 0)
+
+/*--Bit definitions: KS8xx1_BSR */
+#define KS8xx1_100BASE_T4 (1 << 15)
+#define KS8xx1_100BASE_TX_FD (1 << 14)
+#define KS8xx1_100BASE_TX_HD (1 << 13)
+#define KS8xx1_10BASE_T_FD (1 << 12)
+#define KS8xx1_10BASE_T_HD (1 << 11)
+#define KS8xx1_MF_PREAMB_SUPPR (1 << 6)
+#define KS8xx1_AUTONEG_COMP (1 << 5)
+#define KS8xx1_REMOTE_FAULT (1 << 4)
+#define KS8xx1_AUTONEG_ABILITY (1 << 3)
+#define KS8xx1_LINK_STATUS (1 << 2)
+#define KS8xx1_JABBER_DETECT (1 << 1)
+#define KS8xx1_EXTEND_CAPAB (1 << 0)
+
+/*--definitions: KS8xx1_PHYID1 and KS8xx1_PHYID2*/
+#define KS8xx1_OUI 0x0010A1
+
+/*--Bit definitions: KS8xx1_ANAR, KS8xx1_ANLPAR */
+#define KS8xx1_NP (1 << 15)
+#define KS8xx1_ACK (1 << 14)
+#define KS8xx1_RF (1 << 13)
+#define KS8xx1_PAUSE_11 (1 << 11)
+#define KS8xx1_PAUSE_10 (1 << 10)
+#define KS8xx1_T4 (1 << 9)
+#define KS8xx1_TX_FDX (1 << 8)
+#define KS8xx1_TX_HDX (1 << 7)
+#define KS8xx1_10_FDX (1 << 6)
+#define KS8xx1_10_HDX (1 << 5)
+#define KS8xx1_AN_IEEE_802_3 0x01
+
+/*--Bit definitions: KS8xx1_ANER */
+#define KS8xx1_PDF (1 << 4)
+#define KS8xx1_LP_NP_ABLE (1 << 3)
+#define KS8xx1_NP_ABLE (1 << 2)
+#define KS8xx1_PAGE_RX (1 << 1)
+#define KS8xx1_LP_AN_ABLE (1 << 0)
+
+
+/* --Bit definitions: KS8xx1_ICSR */
+#define KS8xx1_JAB_MASK (1 << 15)
+#define KS8xx1_RXERR_MASK (1 << 14)
+#define KS8xx1_PAREC_MASK (1 << 13)
+#define KS8xx1_PDF_MASK (1 << 12)
+#define KS8xx1_LKPAK_MASK (1 << 11)
+#define KS8xx1_LKDWN_MASK (1 << 10)
+#define KS8xx1_REFLT_MASK (1 << 9)
+#define KS8xx1_LKUP_MASK (1 << 8)
+#define KS8xx1_JAB_ISTAT (1 << 7)
+#define KS8xx1_RXERR_ISTAT (1 << 6)
+#define KS8xx1_PAREC_ISTAT (1 << 5)
+#define KS8xx1_PDF_ISTAT (1 << 4)
+#define KS8xx1_LKPAK_ISTAT (1 << 3)
+#define KS8xx1_LKDWN_ISTAT (1 << 2)
+#define KS8xx1_REFLT_ISTAT (1 << 1)
+#define KS8xx1_LKUP_ISTAT (1 << 0)
+
+/****************** function prototypes **********************/
+unsigned int ks8xx1_IsPhyConnected(AT91PS_EMAC p_mac);
+unsigned char ks8xx1_GetLinkSpeed(AT91PS_EMAC p_mac);
+unsigned char ks8xx1_AutoNegotiate(AT91PS_EMAC p_mac, int *status);
+unsigned char ks8xx1_InitPhy(AT91PS_EMAC p_mac);
More information about the U-Boot
mailing list