[U-Boot-Users] [PATCH] Add support for easyToWeb-ARM board
Mirco Fuchs
mircofuchs at web.de
Wed Oct 11 14:22:14 CEST 2006
Hi,
this patch adds support for the AT91RM9200 based easyToWeb-ARM board
(etwarm) developed at the FTZ Leipzig.
The board can be assembled with ether Micrel's PHYs KS8721 or KS8001, or
with Micrel's switches KS8893 or KS8993. To use them, the appropriate driver
patch has to be applied (it was send to this list just before this patch).
Best Regards
Mirco
Signed-off-by: Mirco Fuchs mircofuchs at web.de
CHANGELOG:
- Add support for the AT91RM9200 based easyToWeb-ARM board (etwarm)
diff --git a/MAINTAINERS b/MAINTAINERS
index 4262719..f643d8b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -470,6 +470,9 @@ Alex Züpke <azu at sysgo.de>
lart SA1100
dnp1110 SA1110
+Mirco Fuchs <fuchs at ftz-leipzig.de>
+ etwarm AT91RM9200
+
#########################################################################
# x86 Systems: #
# #
diff --git a/MAKEALL b/MAKEALL
index e9c04a6..1f00a93 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -190,12 +190,12 @@ LIST_ARM9=" \
at91rm9200dk cmc_pu2 \
ap920t ap922_XA10 ap926ejs ap946es \
ap966 cp920t cp922_XA10 cp926ejs \
- cp946es cp966 lpd7a400 mp2usb \
- mx1ads mx1fs2 netstar omap1510inn \
- omap1610h2 omap1610inn omap730p2 sbc2410x \
- scb9328 smdk2400 smdk2410 trab \
- VCMA9 versatile versatileab versatilepb \
- voiceblue \
+ cp946es cp966 etwarm lpd7a400 \
+ mp2usb mx1ads mx1fs2 netstar \
+ omap1510inn omap1610h2 omap1610inn omap730p2 \
+ sbc2410x scb9328 smdk2400 smdk2410 \
+ trab VCMA9 versatile versatileab \
+ versatilepb voiceblue \
"
#########################################################################
diff --git a/Makefile b/Makefile
index 8ef0097..1edb78d 100644
--- a/Makefile
+++ b/Makefile
@@ -1748,6 +1748,8 @@ csb637_config : unconfig
mp2usb_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t mp2usb NULL at91rm9200
+etwarm_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm920t etwarm NULL at91rm9200
########################################################################
## ARM Integrator boards - see doc/README-integrator for more info.
diff --git a/board/etwarm/Makefile b/board/etwarm/Makefile
new file mode 100644
index 0000000..376d833
--- /dev/null
+++ b/board/etwarm/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := etwarm.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/etwarm/config.mk b/board/etwarm/config.mk
new file mode 100644
index 0000000..4c6f631
--- /dev/null
+++ b/board/etwarm/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0x23fc0000
diff --git a/board/etwarm/etwarm.c b/board/etwarm/etwarm.c
new file mode 100644
index 0000000..d945123
--- /dev/null
+++ b/board/etwarm/etwarm.c
@@ -0,0 +1,121 @@
+/*
+ * (C) Copyright 2006 FTZ Leipzig <www.ftz-leipzig.de>
+ * Mirco Fuchs <fuchs at ftz-leipzig.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/AT91RM9200.h>
+#include <at91rm9200_net.h>
+
+#if (CFG_ETH_KS8993)
+#include <ks8993.h>
+#elif (CFG_ETH_KS8893)
+#include <ks8893.h>
+#else /* use CFG_ETH_KS8xx1 */
+#include <ks8xx1.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+ /* Enable Ctrlc */
+ console_init_f ();
+
+ /* memory and cpu-speed are setup before relocation */
+ /* so we do _nothing_ here */
+
+ /* arch number of eTW-ARM-Board */
+ gd->bd->bi_arch_number = MACH_TYPE_ETWARM;
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ return 0;
+}
+
+#define AT91C_PIO_PC15 ((unsigned int) 1 << 15)
+
+int board_late_init (void)
+{
+ /* Enables PIO control of the pin */
+ AT91C_BASE_PIOC->PIO_PER = AT91C_PIO_PC15;
+ /* Set Output Data Register of the pin */
+ AT91C_BASE_PIOC->PIO_SODR = AT91C_PIO_PC15;
+ /* Set Output Enable of the pin */
+ AT91C_BASE_PIOC->PIO_OER = AT91C_PIO_PC15;
+ /* Clear Output Data Register of the pin */
+ AT91C_BASE_PIOC->PIO_CODR = AT91C_PIO_PC15;
+ /* wait 2ms until signal low */
+ udelay(3000);
+ /* Set Output Data Register of the pin */
+ AT91C_BASE_PIOC->PIO_SODR = AT91C_PIO_PC15;
+ AT91C_BASE_PIOC->PIO_ODR = AT91C_PIO_PC15;
+ /* wait 150ms until signal high */
+ udelay(150000);
+}
+
+int dram_init (void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+ return 0;
+}
+
+#ifdef CONFIG_DRIVER_ETHER
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
+
+/*
+ * Name:
+ * at91rm9200_GetPhyInterface
+ * Description:
+ * Initialise the interface functions to the PHY
+ * Arguments:
+ * None
+ * Return value:
+ * None
+ */
+void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
+{
+#if (CFG_ETH_KS8993)
+ p_phyops->Init = ks8993_InitPhy;
+ p_phyops->IsPhyConnected = ks8993_IsPhyConnected;
+ p_phyops->GetLinkSpeed = ks8993_GetLinkSpeed;
+ p_phyops->AutoNegotiate = NULL;
+#elif (CFG_ETH_KS8893)
+ p_phyops->Init = ks8893_InitPhy;
+ p_phyops->IsPhyConnected = ks8893_IsPhyConnected;
+ p_phyops->GetLinkSpeed = ks8893_GetLinkSpeed;
+ p_phyops->AutoNegotiate = NULL;
+#else /* use CFG_ETH_KS8xx1 */
+ p_phyops->Init = ks8xx1_InitPhy;
+ p_phyops->IsPhyConnected = ks8xx1_IsPhyConnected;
+ p_phyops->GetLinkSpeed = ks8xx1_GetLinkSpeed;
+ p_phyops->AutoNegotiate = ks8xx1_AutoNegotiate;
+#endif
+}
+
+#endif /* CONFIG_COMMANDS & CFG_CMD_NET */
+#endif /* CONFIG_DRIVER_ETHER */
diff --git a/board/etwarm/u-boot.lds b/board/etwarm/u-boot.lds
new file mode 100644
index 0000000..76df6b2
--- /dev/null
+++ b/board/etwarm/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj at denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/arm920t/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h
index 7d7888e..22b484b 100644
--- a/include/asm-arm/mach-types.h
+++ b/include/asm-arm/mach-types.h
@@ -737,6 +737,7 @@ #define MACH_TYPE_LN2410SBC 7
#define MACH_TYPE_CB3RUFC 726
#define MACH_TYPE_MP2USB 727
#define MACH_TYPE_PDNB3 1002
+#define MACH_TYPE_ETWARM 1015
#ifdef CONFIG_ARCH_EBSA110
# ifdef machine_arch_type
@@ -9402,6 +9403,18 @@ #else
# define machine_is_mp2usb() (0)
#endif
+#ifdef CONFIG_MACH_ETWARM
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_ETWARM
+# endif
+# define machine_is_etwarm() (machine_arch_type == MACH_TYPE_ETWARM)
+#else
+# define machine_is_etwarm() (0)
+#endif
+
/*
* These have not yet been registered
*/
diff --git a/include/configs/etwarm.h b/include/configs/etwarm.h
new file mode 100644
index 0000000..843a25f
--- /dev/null
+++ b/include/configs/etwarm.h
@@ -0,0 +1,241 @@
+/*
+ * (C) Copyright 2006 FTZ Leipzig <www.ftz-leipzig.de>
+ * Mirco Fuchs <fuchs at ftz-leipzig.de>
+ *
+ * Configuation settings for the eTW-ARM board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* ARM asynchronous clock */
+#define AT91C_MAIN_CLOCK 180000000 /* from 12.000 MHz crystal
(12000000 * 15) */
+#define AT91C_MASTER_CLOCK 45000000 /* (AT91C_MAIN_CLOCK/4)
peripheral clock */
+
+#define AT91_SLOW_CLOCK 32768 /* slow clock */
+
+#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
+#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */
+#define CONFIG_ETWARM 1 /* on a eTW-ARM board */
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+#define USE_920T_MMU 1
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+#define CFG_USE_MAIN_OSCILLATOR 1
+/* flash */
+#define MC_PUIA_VAL 0x00000000
+#define MC_PUP_VAL 0x00000000
+#define MC_PUER_VAL 0x00000000
+#define MC_ASR_VAL 0x00000000
+#define MC_AASR_VAL 0x00000000
+#define EBI_CFGR_VAL 0x00000000
+#define SMC2_CSR_VAL 0x10003185 /* 1 RWHOLD, 16bit, 1 TDF, 5 WS */
+
+/* clocks */
+#define PLLAR_VAL 0x200EBF01 /* 180.000 MHz for PCK */
+#define PLLBR_VAL 0x10083F01 /* 48.000 MHz (divider by 2 for USB) */
+#define MCKR_VAL 0x00000302 /* PCK/4 = MCK Master Clock = 46.000 MHz
from PLLA */
+
+/* sdram */
+#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31)
*/
+#define PIOC_BSR_VAL 0x00000000
+#define PIOC_PDR_VAL 0xFFFF0000
+#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
+#define SDRC_CR_VAL 0x21914159 /* set up the SDRAM */
+#define SDRAM 0x20000000 /* address of the SDRAM */
+#define SDRAM1 0x20000080 /* address of the SDRAM + 128 Bytes,
probably for CFG_GBL_DATA_SIZE*/
+#define SDRAM_VAL 0x00000000 /* value written to SDRAM */
+#define SDRC_MR_VAL 0x00000002 /* Precharge All */
+#define SDRC_MR_VAL1 0x00000004 /* refresh */
+#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
+#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
+#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) /* 128 KiB reserved for
environment data */
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for
initial data */
+
+#define CONFIG_BAUDRATE 115200
+
+/* hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */
+#define CFG_AT91C_BRGR_DIVISOR 75
+
+/*
+ * Hardware drivers
+ */
+
+/* define one of these to choose the DBGU, USART0 or USART1 as console */
+#define CONFIG_DBGU
+#undef CONFIG_USART0
+#undef CONFIG_USART1
+
+#undef CONFIG_HWFLOW /* don't include RTS/CTS flow
control support */
+
+#undef CONFIG_MODEM_SUPPORT /* disable modem initialization
stuff */
+
+#define CONFIG_BOOTDELAY 3
+/* #define CONFIG_ENV_OVERWRITE 1 */
+
+#define CONFIG_COMMANDS \
+ ((CONFIG_CMD_DFL | \
+ CFG_CMD_JFFS2 | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_PING ) & \
+ ~(CFG_CMD_BDI | \
+ CFG_CMD_IMI | \
+ CFG_CMD_AUTOSCRIPT | \
+ CFG_CMD_FPGA | \
+ CFG_CMD_MISC | \
+ CFG_CMD_LOADS ))
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any)
*/
+#include <cmd_confdefs.h>
+
+#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */
+#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */
+
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM 0x20000000
+#define PHYS_SDRAM_SIZE 0x4000000 /* 64 megs */
+
+#define CFG_MEMTEST_START PHYS_SDRAM
+#define CFG_MEMTEST_END CFG_MEMTEST_START +
PHYS_SDRAM_SIZE - 512*1024 - 4
+#define CFG_ALT_MEMTEST 1
+#define CFG_MEMTEST_SCRATCH CFG_MEMTEST_START + PHYS_SDRAM_SIZE
- 4
+
+#define CONFIG_DRIVER_ETHER
+#define CONFIG_NET_RETRY_COUNT 20
+#undef CONFIG_AT91C_USE_RMII
+
+#undef CONFIG_HAS_DATAFLASH
+#define CFG_SPI_WRITE_TOUT (5*CFG_HZ)
+#define CFG_MAX_DATAFLASH_BANKS 0
+#define CFG_MAX_DATAFLASH_PAGES 16384
+#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress
for CS0 */
+#define CFG_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress
for CS3 */
+
+/* #define CONFIG_ETHADDR
+#define CONFIG_IPADDR
+#define CONFIG_NETMASK
+#define CONFIG_SERVERIP
+#define CFG_TFTP_LOADADDR */
+
+/*
+ * Ethernet PHY interface configuration
+ */
+/* definition of ethernet interface (Phy/Switch) - '1' means active*/
+#define CFG_ETH_KS8xx1 0 /* Micrel Phy */
+#define CFG_ETH_KS8893 0 /* Micrel Switch */
+#define CFG_ETH_KS8993 1 /* Micrel Switch */
+
+
+
+/* address of the phy on MII interface, normally (but not necessarily) 0
+ * When using the switch (KS8893), the address has to be 4 (see smi mode as
+ * refernce), because the switch does not support addresses in smi mode,
+ * nevertheless the third address bit has to be set
+ */
+#define CONFIG_PHY_ADDR 0
+
+/* used to reset phy/switch with PC15 after initialization*/
+#define BOARD_LATE_INIT 1
+
+/*
+ * FLASH Device configuration
+ */
+//#define DEBUG 3
+#define PHYS_FLASH_1 0x10000000
+#define PHYS_FLASH_SIZE 0x01000000 /* 16 megs main
flash */
+#define CFG_FLASH_BASE PHYS_FLASH_1
+#define CFG_FLASH_CFI 1 /* flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER 1 /* use common cfi driver */
+#define CFG_FLASH_EMPTY_INFO
+//#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster)
*/
+#define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */
+#define CFG_FLASH_INCREMENT 0 /* there is only one bank */
+#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+
+//#define CFG_FLASH_PROTECTION 1 /* hardware flash protection */
+/*normally 128, but cfi_flash() function on line 1150 is buggy*/
+#define CFG_MAX_FLASH_SECT 256
+
+#define CFG_JFFS2_FIRST_BANK 0
+#define CFG_JFFS2_FIRST_SECTOR 3
+#define CFG_JFFS2_NUM_BANKS 1
+
+#undef CFG_ENV_IS_IN_DATAFLASH
+
+#ifdef CFG_ENV_IS_IN_DATAFLASH
+#define CFG_ENV_OFFSET 0x20000
+#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 +
CFG_ENV_OFFSET)
+#define CFG_ENV_SIZE 0x2000 /* 0x8000 */
+#else
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x20000) /* after
u-boot.bin */
+#define CFG_ENV_SIZE 0x20000 /* sectors are 128K here */
+#endif /* CFG_ENV_IS_IN_DATAFLASH */
+
+
+#define CFG_LOAD_ADDR 0x21000000 /* default load address */
+
+#define CFG_BAUDRATE_TABLE {115200, 57600, 38400, 19200, 9600 }
+
+#define CFG_PROMPT "U-Boot> " /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size
*/
+#define CFG_MAXARGS 16 /* max number of command
args */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print
Buffer Size */
+
+#ifndef __ASSEMBLY__
+/*-----------------------------------------------------------------------
+ * Board specific extension for bd_info
+ *
+ * This structure is embedded in the global bd_info (bd_t) structure
+ * and can be used by the board specific code (eg board/...)
+ */
+
+struct bd_info_ext {
+ /* helper variable for board environment handling
+ *
+ * env_crc_valid == 0 => uninitialised
+ * env_crc_valid > 0 => environment crc in flash is valid
+ * env_crc_valid < 0 => environment crc in flash is invalid
+ */
+ int env_crc_valid;
+};
+#endif
+
+#define CFG_HZ 1000
+#define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is
implicitly set to */
+ /* AT91C_TC_TIMER_DIV1_CLOCK */
+
+#define CONFIG_STACKSIZE (32*1024) /* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif
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