[U-Boot-Users] DDR SDRAM in DIMM module forYosemite-likePPC440EP board.
Stefan Roese
sr at denx.de
Sun Oct 22 13:12:37 CEST 2006
On Sunday 22 October 2006 04:38, Leonid wrote:
> [Leonid] Actually I could make spd_sdram work for my board (our HW guy
> hooked up DIMM EEPROM connections for me). I stepped through code using
> debugger and found out that EEPROM (address 0x51 on our board) has been
> successfully read, all parameters were sane and SDRAM registers have
> been updated accordantly.
OK. So far so good.
> However sdram0_mcsts register's most
> significant bit never becomes 1, meaning SDRAM controller cannot
> complete memory initialization and code stays in endless loop:
>
> /*
> * wait for SDRAM_CFG0_DC_EN to complete
> */
> while (1) {
> mfsdram(mem_mcsts, mcsts);
> if ((mcsts & SDRAM_MCSTS_MRSC) != 0) {
> break;
> }
> }
>
> That looks like HW problem for me.
Yes. I never have seen a board where this did not happen. Did you try to skip
this test to see, if the DDR interface perhaps works without this bit set?
(Just a test of course, no solution).
I have to admit, that I don't know what problems would result in this bit not
being set, apart from DC_EN not set in the SDRAM0_CFG0 register.
> Of course, I'll look through actual
> registers' values more carefully - may be spd_sdram() just parsed EEPROM
> parameters wrongly but I doubt that.
>
> Just in case - did you happen to have BDI config file for that board -
> brief search in the ftp://ftp.denx.de/pub/BDI2000/ directory didn't
> provide results.
Yes. Please find it attached.
Best regards,
Stefan
-------------- next part --------------
;bdiGDB configuration file for IBM 440GX Reference Board
; ------------------------------------------------------
;
[INIT]
; Setup TLB
WTLB 0xF0000095 0x0F00003F ;Boot Space 256MB
WTLB 0x00000094 0x0000003F ;SDRAM 256MB @ 0x00000000
WTLB 0xd0000095 0x2000001B ;PCI Page Entry
WTLB 0xe0000095 0x1400001B ;Peripheral Page Entry
;
; Setup caches
WSPR 0x370 0x00000000 ;INV0
WSPR 0x371 0x00000000 ;INV1
WSPR 0x372 0x00000000 ;INV2
WSPR 0x373 0x00000000 ;INV3
WSPR 0x390 0x00000000 ;DNV0
WSPR 0x391 0x00000000 ;DNV1
WSPR 0x392 0x00000000 ;DNV2
WSPR 0x393 0x00000000 ;DNV3
WSPR 0x398 0x0001f800 ;DVLIM
WSPR 0x399 0x0001f800 ;IVLIM
;
; Setup Peripheral Bus
WDCR 0x12 0x00000010 ;Select EBC0_B0AP
WDCR 0x13 0x04055200 ;B0AP: Flash and SRAM
WDCR 0x12 0x00000000 ;Select EBC0_B0CR
WDCR 0x13 0xfff18000 ;B0CR: 1MB at 0xFFF00000, r/w, 8bit
;WDCR 0x12 0x00000012 ;Select EBC0_B2AP
;WDCR 0x13 0x05055200 ;B2AP: 4 MB Flash
;WDCR 0x12 0x00000002 ;Select EBC0_B2CR
;WDCR 0x13 0xff838000 ;B2CR: 2MB at 0xFFE00000, r/w, 8bit
;
; Setup SDRAM Controller (DDR SDRAM)
WDCR 0x10 0x00000082 ;Select SDRAM0_CLKTR
WDCR 0x11 0x40000000 ;CLKTR: Advance 90 degrees
WDCR 0x10 0x00000080 ;Select SDRAM0_TR0
WDCR 0x11 0x410a4012 ;TR0:
WDCR 0x10 0x00000081 ;Select SDRAM0_TR1
WDCR 0x11 0x8080080b ;TR1:
WDCR 0x10 0x00000040 ;Select SDRAM0_B0CR
WDCR 0x11 0x000a4001 ;B0CR:
WDCR 0x10 0x00000044 ;Select SDRAM0_B1CR
WDCR 0x11 0x080a4001 ;B1CR:
WDCR 0x10 0x00000030 ;Select SDRAM0_RTR
WDCR 0x11 0x04080000 ;RTR:
WDCR 0x10 0x00000020 ;Select SDRAM0_CFG0
WDCR 0x11 0x34000000 ;CFG0: enable SDRAM
WDCR 0x11 0x84000000 ;CFG0: enable SDRAM
DELAY 100
;
; Setup default vector table
WSPR 0x03f 0x00000000 ;IVPR vector base at 0x00000000
WSPR 0x190 0x00000100 ;IVOR0 Critical Input
WSPR 0x191 0x00000200 ;IVOR1 Machine Check
WSPR 0x192 0x00000300 ;IVOR2 Data Storage
WSPR 0x193 0x00000400 ;IVOR3 Instruction Storage
WSPR 0x194 0x00000500 ;IVOR4 External Input
WSPR 0x195 0x00000600 ;IVOR5 Alignment
WSPR 0x196 0x00000700 ;IVOR6 Program
WSPR 0x197 0x00000800 ;IVOR7 Reserved
WSPR 0x198 0x00000c00 ;IVOR8 System Call
WSPR 0x199 0x00000a00 ;IVOR9 Reserved
WSPR 0x19a 0x00001000 ;IVOR10 Decrementer
WSPR 0x19b 0x00001010 ;IVOR11 Fixed Interval Timer
WSPR 0x19c 0x00001020 ;IVOR12 Watchdog Timer
WSPR 0x19d 0x00001100 ;IVOR13 Data TLB Error
WSPR 0x19e 0x00001200 ;IVOR14 Instruction TLB Error
WSPR 0x19f 0x00000f00 ;IVOR15 Debug
;
; Clear DBCR1 and DBCR2
WSPR 0x135 0x00000000 ;DBCR1
WSPR 0x136 0x00000000 ;DBCR2
[TARGET]
JTAGCLOCK 0 ;use 16 MHz JTAG clock
CPUTYPE 440 ;the used target CPU type
SCANMISC 8 ;IR length is 8 bits for 440GX
WAKEUP 50 ;wakeup time after reset
;BREAKMODE SOFT ;SOFT or HARD, HARD uses PPC hardware breakpoint
BREAKMODE HARD ;SOFT or HARD, HARD uses PPC hardware breakpoint
STEPMODE JTAG ;JTAG or HWBP, HWBP uses one or two hardware breakpoints
;MMU XLAT 0xC0000000 ;enable virtual address mode
;PTBASE 0x00000000 ;address where kernel/user stores pointer to page table
;SIO 7 9600 ;TCP port for serial IO
;REGLIST ALL ;select register to transfer to GDB
[HOST]
IP 192.168.1.1
FILE /tftpboot/yosemite/u-boot.bin
FORMAT BIN
DUMP /tftpboot/yosemite/dump.bin
PROMPT 440EP>
[FLASH]
; user flash at 0xff800000, AM29LV033C (4M x 8)
;WORKSPACE 0xFF800000 ;workspace in SRAM for fast programming algorithm
;WORKSPACE 0x00100000 ;workspace in SDRAM for fast programming algorithm
;CHIPTYPE AM29BX16 ;Flash type (AM29F | AM29BX8 | AM29BX16 | I28BX8 | I28BX16)
CHIPTYPE AM29F ;Flash type (AM29F | AM29BX8 | AM29BX16 | I28BX8 | I28BX16)
CHIPSIZE 0x80000 ;The size of one flash chip in bytes
BUSWIDTH 8 ;The width of the flash memory bus in bits (8 | 16 | 32)
FILE /tftpboot/pcs440ep/u-boot.bin
FORMAT BIN 0xFFFA0000
;ERASE 0xFFF80000 ;erase sector
;ERASE 0xFFF90000 ;erase sector
ERASE 0xFFFA0000 ;erase sector
ERASE 0xFFFB0000 ;erase sector
ERASE 0xFFFC0000 ;erase sector
ERASE 0xFFFD0000 ;erase sector
ERASE 0xFFFE0000 ;erase sector
ERASE 0xFFFF0000 ;erase sector
[REGS]
IDCR1 0x010 0x011 ;SDRAM0_CFGADDR and SDRAM0_CFGDATA
IDCR2 0x012 0x013 ;EBC0_CFGADDR and EBC0_CFGDATA
IDCR3 0x014 0x015 ;EBM0_CFGADDR and EBM0_CFGDATA
IDCR4 0x016 0x017 ;PPM0_CFGADDR and PPM0_CFGDATA
IDCR5 0x00C 0x00D ;CPR0_CFGADDR and CPR0_CFGDATA
IDCR6 0x00E 0x00F ;SDR0_CFGADDR and SDR0_CFGDATA
DMM1 0xD0000000 ;PCI (should map to 2_000_0000)
DMM2 0xE0000000 ;Peripheral (should map to 1_400_0000)
FILE /tftpboot/BDI2000/reg440gx.def
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