[U-Boot-Users] DDR SDRAM in DIMM module forYosemite-likePPC440EP board.

[Leonid]

On Sunday, October 22, 2006 4:13 AM Stefan Roese wrote:
> > Actually I could make spd_sdram work for my board (our HW guy
> > hooked up DIMM EEPROM connections for me). I stepped through code
using
> > debugger and found out that EEPROM (address 0x51 on our board) has
been
> > successfully read, all parameters were sane and SDRAM registers have
> > been updated accordantly.

> OK. So far so good.

> > However sdram0_mcsts register's most 
> > significant bit never becomes 1, meaning SDRAM controller cannot
> > complete memory initialization and code stays in endless loop:
> > That looks like HW problem for me.

> Yes. I never have seen a board where this did not happen. Did you try
to 
> skip this test to see, if the DDR interface perhaps works without this
bit 
> set? (Just a test of course, no solution).

[Leonid] It was first thing I tried - just leave the loop after 1 mln
loops even if status is not ready. It fails on memory test in
program_tr1() function. I'll work with our HW folks to see what can be
done.

Best regards,
Leonid.