[U-Boot-Users] Still trying to get a stable running on 8349ITX evalboard

Bruce_Leonard at selinc.com Bruce_Leonard at selinc.com
Tue Apr 17 02:10:55 CEST 2007

"Benedict, Michael" <MBenedict at twacs.com> wrote on 04/16/2007 02:25:14 PM:

> > 
> The key differences were:
> DDR:timing_cfg_1=0x26242321
> <snip>
> DDR:sdram_mode=0x00000032
> For the hard-coded RAM init / stable case and
> DDR:timing_cfg_1=0x26232321
> <snip>
> DDR:sdram_mode=0x00000022

I found the same descrepency.  I'm used to SDRAM, but I'm still figuring 
out DDR SDRAM (which is just enough different to be confusing ;)  ) so I'm 
not sure what impact the differences in timing_cfg_1 have.  Working on it.

> I am really confused by this code.  Hopefully someone can explain all
> the conditionals that are causing the caslat to be decremented based on

I'm right there with you, but I'm going through the code line by line 
trying to figure out what it's doing.  Then I'm going to post about a 
thousand (well maybe only a few) specific questions.  Hopefully the 
answers to those will help clear up both or our confusions.  I'm seeing 
some really tricky stuff in here, but I'm not sure but what that tricky 
stuff is what's causing our problems.  Update again tomorrow.



This e-mail may contain SEL confidential information.  The opinions
expressed are not necessarily those of SEL.  Any unauthorized disclosure,
distribution or other use is prohibited.  If you received this e-mail in
error, please notify the sender, permanently delete it, and destroy any

Thank you.


More information about the U-Boot mailing list