[U-Boot-Users] Still trying to get a stable 2.6.20.4 running on 8349ITX evalboard

[Bruce_Leonard at selinc.com]

Timur Tabi <timur at freescale.com> wrote on 04/13/2007 10:03:29 AM:

> Bruce_Leonard at selinc.com wrote:
> 
> > Just an update, I've had the kernel up and running a continuos "find" 
> > command for the last 11 hours using the hardcoded DDR memory 
controller 
> > values, so there's definitely something wrong with using SPD and the 
> > memory that's installed on my 8349itx board.  Still working on 
figuring 
> > out spd_sdram().
> 
> You may need to define CFG_DDR_SDRAM_CLK_CNTL.
> 
Well, I finally zeroed in on the problem and it is indeed the DDR SDRAM 
Clock Control register as Timur suggested nearly a week ago, I just didn't 
understand at the time what he was saying.  Evidently the msb of this 
register needs to be set for DDR memory to work correctly on the 834x. 
However, I have three (and only three :)  ) questions:

1) Since it clearly needs to be set so that DDR memory will work (and I 
can see in a few other config files where CFG_DDR_SDRAM_CLK_CNTL gets that 
high bit set), why does the MPC8349ITX config file NOT set it and how has 
it worked for so many people for so long?  I find it difficult to believe 
that I'm the first person to stumble over this.  Or am I the only person 
who has tried to use the SPD code on this board?
2) My major concern is this: that high bit is un-documented, it's shown as 
reserverd in all the documentation I can find for the 834x.  How was I (or 
anyone for that matter) supposed to know about that bit?
3) What exactly is the purpose of "providing a source-synchronous option"? 
 That collection of words doesn't mean anything to me.

Thanks to all that helped point me in the right direction on this one.  I 
could have spent many weeks digging into/blaming the kernel before I ever 
thought of RAM problems.

Bruce


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