[U-Boot-Users] Still trying to get a stable 2.6.20.4 running on 8349ITX evalboard

[Benedict, Michael]

Bruce_Leonard at selinc.com wrote:
> 1) Since it clearly needs to be set so that DDR memory will
> work (and I
> can see in a few other config files where
> CFG_DDR_SDRAM_CLK_CNTL gets that
> high bit set), why does the MPC8349ITX config file NOT set it
> and how has
> it worked for so many people for so long?  I find it
> difficult to believe
> that I'm the first person to stumble over this.  Or am I the
> only person
> who has tried to use the SPD code on this board?

Actually, the clock control used to be set to this value, until commit
f6eda7f80ccc13d658020268c507d7173cf2e8aa in October last year.  The
Freescale-release BSP also has sdram_clk_cntl set to this value. I am
curious if the change was intended to accommodate another platform or if
there is something more going on here.
	Cheers,
		Michael