[U-Boot-Users] Still trying to get a stable 2.6.20.4 running on 8349ITX evalboard

[Bruce_Leonard at selinc.com]

"Benedict, Michael" <MBenedict at twacs.com> wrote on 04/20/2007 11:13:21 AM:

> 
> Actually, the clock control used to be set to this value, until commit
> f6eda7f80ccc13d658020268c507d7173cf2e8aa in October last year.  The
> Freescale-release BSP also has sdram_clk_cntl set to this value. I am
> curious if the change was intended to accommodate another platform or if
> there is something more going on here.
>    Cheers,
>       Michael
> 

Okay Micheal,

How the #$^@&#$%&@^$ did you figure out which commit changed things?  I 
don't even know how to find that commit so I can see what changed!  The 
way I see the issue being 'fixed' is to have the following in 
.../include/configs/MPC8349ITX.h:

#define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | 
DDR_SDRAM_CLK_CNTL_ADJUST_05)

At least that's what I did to fix it and i just lifted that from Timur's 
hardcoded SDRAM init routine in .../board/mpc8349itx/mpc8349itx.c.  By 
doing the above in the config file you cause spd_sdram() to load 
CFG_DDR_SDRAM_CLK_CNTL into the clock control register and everything 
works fine.  But I can't find that the above has ever been done in the 
config file.  It certainly wasn't in (what appears to me anyway but I 
don't know how to drive git so I may be mistaken) the original posting of 
the config file.  And I don't think it's been in any version since.  So I 
don't think using spd_sdram() to set up the DDR controller on the 8349itx 
board has ever worked.

To follow up on the purpose of the register, it provides a way to adjust 
your DDR clock (CLK not CLK\) relative to when the DDR command/address is 
issued (see Freescale's app note AN2583).  Has something to do with the 
way the DDR controller's clock is locked or not locked with DLL.  I don't 
really follow it all yet, but it's one more way to adjust signals so that 
everything lines up correctly for setup and hold times.  However, for our 
purposes of getting this board to work using spd_sdram(), you do need to 
setup the clock control reg with the values noted above, provided you are 
using a Kingston KVR400X64C3A/256 DDR memory module like I am.  I don't 
gaurentee that the adjust value will be correct for any other part.

Hope this helps someone other than just me, given how long this thread has 
been going on.  :)

Bruce

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