[U-Boot-Users] changes for IDS8247 Board

Sergej Stepanov Sergej.Stepanov at ids.de
Thu Aug 2 13:03:44 CEST 2007


Hallo,

we did some changes for u-boot-1.2.0 to support our IDS8247 board.

Thanks and regards.
---
Sergej I. Stepanov
IDS GmbH
Nobelstr. 18
D-76275 Ettlingen
T +49 (0) 72 43/2 18-615
F +49 (0) 72 43/2 18-400
http://www.ids.de
Email: Sergej.Stepanov at ids.de
--------

diff -rpuN u-boot-1.2.0_orig/board/ids8247/ids8247.c u-boot-1.2.0_IDS8247/board/ids8247/ids8247.c
--- u-boot-1.2.0_orig/board/ids8247/ids8247.c	2007-01-07 00:13:11.000000000 +0100
+++ u-boot-1.2.0_IDS8247/board/ids8247/ids8247.c	2007-08-02 12:24:49.000000000 +0200
@@ -19,12 +19,20 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
+ *
+ * FCC1 was activated and FCC2 was deactivated for IDS8247 platform
+ * Sergej Stepanov, IDS GmbH, Germany, <Sergej.Stepanov at ids.de>
+ *
  */
 
 #include <common.h>
 #include <ioports.h>
 #include <mpc8260.h>
 
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+#endif
+
 DECLARE_GLOBAL_DATA_PTR;
 
 /*
@@ -38,12 +46,12 @@ const iop_conf_t iop_conf_tab[4][32] = {
 
     /* Port A configuration */
     {	/*	      conf ppar psor pdir podr pdat */
-	/* PA31 */ {   0,   1,	 1,   0,   0,	0   }, /* FCC1 COL */
-	/* PA30 */ {   0,   1,	 1,   0,   0,	0   }, /* FCC1 CRS */
-	/* PA29 */ {   0,   1,	 1,   1,   0,	0   }, /* FCC1 TXER */
-	/* PA28 */ {   0,   1,	 1,   1,   0,	0   }, /* FCC1 TXEN */
-	/* PA27 */ {   0,   1,	 1,   0,   0,	0   }, /* FCC1 RXDV */
-	/* PA26 */ {   0,   1,	 1,   0,   0,	0   }, /* FCC1 RXER */
+	/* PA31 */ {   1,   1,	 1,   0,   0,	0   }, /* FCC1 COL */
+	/* PA30 */ {   1,   1,	 1,   0,   0,	0   }, /* FCC1 CRS */
+	/* PA29 */ {   1,   1,	 1,   1,   0,	0   }, /* FCC1 TXER */
+	/* PA28 */ {   1,   1,	 1,   1,   0,	0   }, /* FCC1 TXEN */
+	/* PA27 */ {   1,   1,	 1,   0,   0,	0   }, /* FCC1 RXDV */
+	/* PA26 */ {   1,   1,	 1,   0,   0,	0   }, /* FCC1 RXER */
 	/* PA25 */ {   0,   0,	 0,   0,   1,	0   }, /* 8247_P0 */
 #if defined(CONFIG_SOFT_I2C)
 	/* PA24 */ {   1,   0,	 0,   0,   1,	1   }, /* I2C_SDA2 */
@@ -53,14 +61,14 @@ const iop_conf_t iop_conf_tab[4][32] = {
 	/* PA23 */ {   0,   0,	 0,   1,   0,	0   }, /* PA23 */
 #endif
 	/* PA22 */ {   0,   0,	 0,   0,   1,	0   }, /* SMC2_DCD */
-	/* PA21 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 TXD3 */
-	/* PA20 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 TXD2 */
-	/* PA19 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 TXD1 */
-	/* PA18 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC1 TXD0 */
-	/* PA17 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 RXD0 */
-	/* PA16 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 RXD1 */
-	/* PA15 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 RXD2 */
-	/* PA14 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC1 RXD3 */
+	/* PA21 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC1 TXD3 */
+	/* PA20 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC1 TXD2 */
+	/* PA19 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC1 TXD1 */
+	/* PA18 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC1 TXD0 */
+	/* PA17 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC1 RXD0 */
+	/* PA16 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC1 RXD1 */
+	/* PA15 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC1 RXD2 */
+	/* PA14 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC1 RXD3 */
 	/* PA13 */ {   0,   0,	 0,   1,   1,	0   }, /* SMC2_RTS */
 	/* PA12 */ {   0,   0,	 0,   0,   1,	0   }, /* SMC2_CTS */
 	/* PA11 */ {   0,   0,	 0,   1,   1,	0   }, /* SMC2_DTR */
@@ -79,20 +87,20 @@ const iop_conf_t iop_conf_tab[4][32] = {
 
     /* Port B configuration */
     {	/*	      conf ppar psor pdir podr pdat */
-	/* PB31 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TX_ER */
-	/* PB30 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_DV */
-	/* PB29 */ {   1,   1,	 1,   1,   0,	0   }, /* FCC2 MII TX_EN */
-	/* PB28 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_ER */
-	/* PB27 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII COL */
-	/* PB26 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII CRS */
-	/* PB25 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[3] */
-	/* PB24 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[2] */
-	/* PB23 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[1] */
-	/* PB22 */ {   1,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[0] */
-	/* PB21 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[0] */
-	/* PB20 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[1] */
-	/* PB19 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[2] */
-	/* PB18 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[3] */
+	/* PB31 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC2 MII TX_ER */
+	/* PB30 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_DV */
+	/* PB29 */ {   0,   1,	 1,   1,   0,	0   }, /* FCC2 MII TX_EN */
+	/* PB28 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_ER */
+	/* PB27 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC2 MII COL */
+	/* PB26 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC2 MII CRS */
+	/* PB25 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[3] */
+	/* PB24 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[2] */
+	/* PB23 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[1] */
+	/* PB22 */ {   0,   1,	 0,   1,   0,	0   }, /* FCC2 MII TxD[0] */
+	/* PB21 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[0] */
+	/* PB20 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[1] */
+	/* PB19 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[2] */
+	/* PB18 */ {   0,   1,	 0,   0,   0,	0   }, /* FCC2 MII RxD[3] */
 	/* PB17 */ {   0,   0,	 0,   0,   0,	0   }, /* PB17 */
 	/* PB16 */ {   0,   0,	 0,   0,   0,	0   }, /* PB16 */
 	/* PB15 */ {   0,   0,	 0,   0,   0,	0   }, /* PB15 */
@@ -123,8 +131,8 @@ const iop_conf_t iop_conf_tab[4][32] = {
 	/* PC26 */ {   0,   0,	 0,   1,   0,	0   }, /* PC26 */
 	/* PC25 */ {   0,   1,	 1,   0,   0,	0   }, /* SYNC_IN */
 	/* PC24 */ {   0,   0,	 0,   1,   0,	0   }, /* PC24 */
-	/* PC23 */ {   0,   1,	 0,   1,   0,	0   }, /* ATMTFCLK */
-	/* PC22 */ {   0,   1,	 0,   0,   0,	0   }, /* ATMRFCLK */
+	/* PC23 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC1 MII TX_CLK */
+	/* PC22 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC1 MII RX_CLK */
 	/* PC21 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN RXCLK */
 	/* PC20 */ {   0,   1,	 0,   0,   0,	0   }, /* SCC1 EN TXCLK */
 	/* PC19 */ {   1,   1,	 0,   0,   0,	0   }, /* FCC2 MII RX_CLK */
@@ -180,7 +188,7 @@ const iop_conf_t iop_conf_tab[4][32] = {
 	/* PD10 */ {   0,   0,	 0,   0,   0,	0   }, /* PD10 */
 	/* PD9	*/ {   0,   0,	 0,   0,   0,	0   }, /* PD9 */
 	/* PD8	*/ {   0,   0,	 0,   0,   0,	0   }, /* PD8 */
-	/* PD7	*/ {   0,   0,	 0,   1,   0,	1   }, /* MII_MDIO */
+	/* PD7	*/ {   1,   0,	 0,   1,   0,	1   }, /* MII_MDIO */
 	/* PD6	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD6 */
 	/* PD5	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD5 */
 	/* PD4	*/ {   0,   0,	 0,   1,   0,	1   }, /* PD4 */
@@ -224,7 +232,7 @@ static long int try_init (volatile memct
 	 * mapped by the controller. That means, that the initial mapping has
 	 * to be (at least) twice as large as the maximum expected size.
 	 */
-	maxsize = (1 + (~orx | 0x7fff)) / 2;
+	maxsize = (1 + (~orx | 0x7fff))/* / 2*/;
 
 	sdmr_ptr = &memctl->memc_psdmr;
 	orx_ptr = &memctl->memc_or2;
@@ -316,3 +324,28 @@ nand_init (void)
 }
 
 #endif	/* CFG_CMD_NAND */
+
+#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+	u32 *p;
+	int len;
+	ulong clock;
+	/* do what ft_cpu_setup does */
+
+	clock = bd->bi_busfreq;
+	p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
+	if (p != NULL)
+		*p = cpu_to_be32(clock);
+
+	p = ft_get_prop(blob, "/" OF_SOC "/console at 0000/clock-frequency", &len);
+		memcpy(p, bd->bi_enetaddr, 6);
+
+	p = ft_get_prop(blob, "/memory/reg", &len);
+	if (p != NULL) {
+		*p++ = cpu_to_be32(bd->bi_memstart);
+		*p = cpu_to_be32(bd->bi_memsize);
+	}
+}
+#endif
diff -rpuN u-boot-1.2.0_orig/include/configs/IDS8247.h u-boot-1.2.0_IDS8247/include/configs/IDS8247.h
--- u-boot-1.2.0_orig/include/configs/IDS8247.h	2007-01-07 00:13:11.000000000 +0100
+++ u-boot-1.2.0_IDS8247/include/configs/IDS8247.h	2007-08-02 12:25:07.000000000 +0200
@@ -19,6 +19,13 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
+ *
+ * for IDS8247 platform
+ *  - FCC1 is activated
+ *  - FCC2 is deactivated 
+ *  - I2C is activated
+ * Sergej Stepanov, IDS GmbH, Germany, <Sergej.Stepanov at ids.de>
+ *
  */
 
 /*
@@ -27,7 +34,7 @@
 
 #ifndef __CONFIG_H
 #define __CONFIG_H
-
+#undef DEBUG
 /*
  * High Level Configuration Options
  * (easy to change)
@@ -120,6 +127,20 @@
 
 #define CFG_NS16550_COM1        (CFG_UART_BASE + 0x8000)
 
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE   1
+#define CONFIG_OF_BOARD_SETUP 1
+
+/* maximum size of the flat tree (8K) */
+//#define OF_FLAT_TREE_MAX_SIZE 8192
+
+#define OF_CPU "PowerPC,8247 at 0"
+#define OF_SOC "soc8247 at e0008000"
+#define OF_TBCLK (bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH "/soc8247 at e0008000/console at 0000"
+
+
 /*
  * select ethernet configuration
  *
@@ -135,8 +156,22 @@
 #undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
 #define	CONFIG_ETHER_ON_FCC		/* define if ether on FCC       */
 #undef	CONFIG_ETHER_NONE		/* define if ether on something else */
-#define	CONFIG_ETHER_INDEX    2		/* which SCC/FCC channel for ethernet */
+#define	CONFIG_ETHER_INDEX    1		/* which SCC/FCC channel for ethernet */
+#define CONFIG_ETHER_ON_FCC1
+#define FCC_ENET
 
+#if 1 /* FCC */
+/*
+ * - Rx-CLK is CLK10
+ * - Tx-CLK is CLK9
+ * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+# define CFG_CMXFCR_MASK	(CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
+# define CFG_CMXFCR_VALUE	(CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK9)
+# define CFG_CPMFCR_RAMTYPE	0
+# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
+#else
 /*
  * - Rx-CLK is CLK13
  * - Tx-CLK is CLK14
@@ -147,7 +182,7 @@
 # define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
 # define CFG_CPMFCR_RAMTYPE	0
 # define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)
-
+#endif
 
 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
 #define CONFIG_8260_CLKIN	66666666	/* in Hz */
@@ -161,7 +196,12 @@
 
 #define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
 
+#define CONFIG_RTC_PCF8563
+#define CFG_I2C_RTC_ADDR		0x51
+
 #define CONFIG_COMMANDS	       (CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DATE	| \
 				CFG_CMD_DHCP	| \
 				CFG_CMD_NFS	| \
 				CFG_CMD_NAND	| \
@@ -203,7 +243,10 @@
  */
 #define CFG_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
 
-
+#define CFG_FLASH_CFI                           /* The flash is CFI compatible  */
+#define CFG_FLASH_CFI_DRIVER                    /* Use common CFI driver        */
+#define CFG_FLASH_BANKS_LIST { 0xFF800000 }
+#define CFG_MAX_FLASH_BANKS_DETECT 1
 /* What should the base address of the main FLASH be and how big is
  * it (in MBytes)? This must contain TEXT_BASE from board/ids8247/config.mk
  * The main FLASH is whichever is connected to *CS0.
@@ -219,7 +262,7 @@
  * FLASH organization
  */
 #define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
-#define CFG_MAX_FLASH_SECT	64	/* max num of sects on one chip */
+#define CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/
 
 #define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
 #define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */
@@ -496,17 +539,23 @@
 			 BRx_MS_SDRAM_P                 |\
 			 BRx_V)
 
-#define CFG_OR2_PRELIM	CFG_OR2
 
 
 /* SDRAM initialization values
 */
-#define CFG_OR2    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+/*#define CFG_OR2    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |	\
 			 ORxS_BPD_4                     |\
 			 ORxS_ROWST_PBI0_A10             |\
 			 ORxS_NUMR_12)
+*/
+#define CFG_OR2    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
+			 ORxS_BPD_4                     |\
+			 ORxS_ROWST_PBI0_A9             |\
+			 ORxS_NUMR_12)
+
+#define CFG_OR2_PRELIM	CFG_OR2
 
-#define CFG_PSDMR  (PSDMR_SDAM_A13_IS_A5 |\
+/*#define CFG_PSDMR  (PSDMR_SDAM_A13_IS_A5 |		\
 			 PSDMR_BSMA_A15_A17           |\
 			 PSDMR_SDA10_PBI0_A11         |\
 			 PSDMR_RFRC_5_CLK               |\
@@ -516,6 +565,17 @@
 			 PSDMR_LDOTOPRE_2C              |\
 			 PSDMR_WRC_3C                   |\
 			 PSDMR_CL_3)
+*/
+#define CFG_PSDMR  (PSDMR_SDAM_A14_IS_A5 |\
+			 PSDMR_BSMA_A15_A17           |\
+			 PSDMR_SDA10_PBI0_A10         |\
+			 PSDMR_RFRC_5_CLK               |\
+			 PSDMR_PRETOACT_2W              |\
+			 PSDMR_ACTTORW_2W               |\
+			 PSDMR_BL                       |\
+			 PSDMR_LDOTOPRE_2C              |\
+			 PSDMR_WRC_3C                   |\
+			 PSDMR_CL_3)
 
 /* Bank 3 - UART
 */





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