[U-Boot-Users] RFC: Xilinx Spartan3 relocation code

[Matthias Fuchs]

Laurent,

I think we are talking about different types of bitstreams.
That's why I ask for the image type before.

In my understanding bitstream are those files that are generated 
by xilinx' bitgen tool. Those files always have the same bit order.
You can use U-Boot's fpga load command to download them to FPGAs
in slave serial mode. The left bit is shifted out first.

For these bitstreams it is much nicer to use the loadb option, because it
pretty prints the bitstream's header.

I noticed that you can also use the xilinx promgen tool to generate a 
programming file (I do not use those files). These files can (and need not)
have a different bit order. But do they have the nice header that is 
printed by loadb? 

So what kind of images/bitstreams are you talking about? Do we really need
to support all of them?

Matthias

On Tuesday 21 August 2007 11:04, Laurent Pinchart wrote:
> Hi Matthias,
> 
> On Tuesday 21 August 2007 10:52, Matthias Fuchs wrote:
> > Bruce,
> >
> > what kind of bitstream file do you download to your FPGA?
> > A .bit File? In this case we should put the bit mirroring into the
> > wdata() callback or the *_sp_load() function, because the serial slave
> > download is fine without mirroring.
> 
> You can't do that. Data should be mirrored only if they come from bitstreams 
> (fpga loadb). PROM files are already mirrored. The wdata() callback would 
> then have to mirror the bits only for "fpga loadb" and not for "fpga load", 
> but that information is not available in the callback.
> 
> > Any way there is not need to malloc 
> > a very huge amount of memory an do the mirroring on a buffer. This
> > can be done on-the-fly during download.
> >
> > Matthias
> >
> > On Monday 20 August 2007 19:46, Bruce_Leonard at selinc.com wrote:
> > > Stefan,
> > >
> > > > > > I fixed and added some things for the generic FPGA boot. Patches
> > >
> > > will be
> > >
> > > > > > posted with the new board patch.
> > >
> > > Sorry for the late reply, had a big BBQ this weekend for my anniversary
> > > and haven't checked my e-mail in three or four days.  Could you please
> > > let me know what your patches are going to look like?  I don't want to
> > > push up any patches that will cover/conflict things you've got in your
> > > queue.
> > >
> > > > > trouble getting the FPGA to program.  We're currently assuming that
> > >
> > > our
> > >
> > > > > interface to the FPGA is broken, but if there's known issues in the
> > > > > generic code that would be nice to know :).
> > >
> > > I finally figured out what stupid thing I was doing.  Both the FPGA and
> > > the PPC are big endian, however if the processor is little endian the
> > > data needs to be bit-swapped before going to the FPGA over SelectMap. 
> > > When I was commenting out the code to do the bit-swapping (which we don't
> > > need to do) I got over zealous by one line and wasn't initializing a
> > > pointer.  So I was sending nothing but 0x24 to the FPGA.  Wonder why it
> > > didn't program?
> > >
> > > :0
> > >
> > > I'm going to try and come up with a clean way (probably a config option)
> > > of doing or not doing the bit-swap thing in code.  If you're running a
> > > bit endian system you really don't need or want to do it.  Little endian
> > > systems, unless you're very carefull with your HW design, you want to do
> > > it.  I'll have a patch for it in a couple of days.  I was thinking
> > > something along the lines of "#define CFG_NO_SELECTMAP_BITSWAP".  If it's
> > > not defined the code does the bit-swap, which is the way everything
> > > currently works.  Or should it be a CONFIG instead?
> > >
> > > Bruce
> >
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