[U-Boot-Users] Some RFCs about U-Boot's the generic FPGA support
Laurent Pinchart
laurentp at cse-semaphore.com
Wed Aug 22 09:28:36 CEST 2007
Hi Bruce,
On Tuesday 21 August 2007 22:09, Bruce_Leonard at selinc.com wrote:
> > Bit mirroring might not be needed in slave serial mode, but is
> > needed in slave parallel mode. Bytes in the .bit file are stored with the
> > LSB on the left side. The bytes must then be reversed before being written
> > in slave parallel mode, as the FPGA expects the LSB on D0, not on D7.
>
> Again, it depends on the processor you are using and how it's hooked up to
> the FPGA. BTW, according to the Spartan 3 data sheet "data bit D0 is the
> MOST-significant (msb) bit and D7 is the least-significant bit (lsb)" (pg
> 167, Xilinx UG332 Spartan-3 Generation confiuration User Guide). Maybe
> you are refering to a different FPGA?
Ok. You're right. The Spartan-3E datasheet (DS312) was silent about the bit
ordering. UG322 sheds some light on the issue. D0-D7 are indeed MSB-LSB,
making the SelectMAP interface use the big-endian PPC bit ordering
convention.
> > Without mirroring, bitstreams won't load in slave parallel mode. You
> > should keep mirroring, and change the slave serial code to shift bits the
> > other way around.
>
> I must respectfully disagree. In my design, if I mirror in the code the
> FPGA does NOT load. In a PPC, D0 is the MSB, NOT the LSB. In a Spartan 3
> FPGA, D0 is the MSB, NOT the LSB. Therefore if you connect your bus
> straight across between the PPC and the Spartan 3 FPGA, AND do mirroring
> in the code, your FPGA will not load.
I got a similar design, except that D0-D7 on the PPC are connected to D7-D0 on
the FPGA. I'll go scold our hardware engineer :-)
With a properly connected bus between the processor and the FPGA, bit reversal
is thus not needed when loading a .bit file (fpga loadb) or a non mirrored
PROM file (fpga load).
For hardware with bit mirroring on the bus, I suggest either using a mirrored
PROM file or mirroring the bit in the data write callback. I thus vote for
removing bit mirroring in fpga_loadbitstream() and adding an explanation of
this issue (either in the code or in the documentation) to prevent hardware
mistakes in future designs.
Best regards,
--
Laurent Pinchart
CSE Semaphore Belgium
Chaussée de Bruxelles, 732A
B-1410 Waterloo
Belgium
T +32 (2) 387 42 59
F +32 (2) 387 42 75
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