[U-Boot-Users] question of codes in \cpu\74xx_7xx\cache.S

[xiangguo_li at hotmail.com]

thank you. you are right.
I find the reason in the manual: 
DCE 2 Data cache enable
0 The data cache is neither accessed nor updated. All pages are accessed as if they were
marked cache-inhibited (WIM = x1x). Potential cache accesses from the bus (snoop and cache
operations) are ignored. In the disabled state for the L1 caches, the cache tag state bits are
ignored and all accesses are propagated to the L2 cache, L3 cache, or bus as cache-inhibited.
For those transactions, CI is asserted regardless of address translation.DCE is zero at
power-up.
1 The data cache is enabled.Note that HID0[DCFI] must be set at the same time that this bit is set.
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Most likely neither are redundant.  To say for sure, you need to read 
the User's Manual for the 74xx family where it specifies how to change 
the HID0 register
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HTH,
gvb
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