[U-Boot-Users] minimum bdi config to read flash on 85xx

[robert lazarski]

Hi all,

On our custom 8548 board, we can't read our flash correctly. We have
one 1Gb bank of spansion S29GL01GP flash and we get:

atum>mdh 0xf8000000
0_f8000000 : f9f7 f9f7 f9f7 f9f7 f9f7 f9f7 f9f7 f9f7

The big problem we have now: is this a hardware issue or a bdi config
issue? Aside from the flash we have 1GigaByte of DDR ram. Can anyone
help us track our flash issues down to be hardware, config file, or
some combination? The hardware guys think the board is fine. We've
been deep into the manuals of both the 8548 and the bdi and can't find
anything wrong. Here's the config, thanks for any help!

;bdiGDB configuration file for ATUM 8548
;---------------------------------------------------
;
[INIT]
;
;
; use the following two lines for STARTUP HALT
WSPR    63              0xffff0000      ;IVPR to boot core
WSPR    415             0x0000f000      ;IVOR15 : Debug exception
;
;
;================= setup for flash programming ===============
; Move CCSRBAR to 0xe0000000
WM32    0xff700000      0x000e0000      ;CCSRBAR to 0xe0000000
;
; Initialize LAWBAR's
WM32    0xe0000C08      0x00000000      ;LAWBAR0 : @0x00000000
WM32    0xe0000C10      0x80f0001d      ;LAWAR0  : DDR 1GB
WM32    0xe0000C28      0xf8000000      ;LAWBAR1 : @0xf8000000
WM32    0xe0000C30      0x8040001a      ;LAWAR1  : Local Bus  128MB
for S29GL01GP
;
; Setup Flash chip select
WM32    0xe0005000      0xf8001001      ;BR0
WM32    0xe0005004      0xf8000E65      ;OR0

; CS0_BNDS
WM32 	0xe0002000 0x0000000f ; DDR CS0

; CS0_CONFIG
WM32 	0xe0002080 0x80000102

; TIMING_CFG_0
WM32	0xe0002104 0x00260802

; TIMING_CFG_1
WM32	0xe0002108 0x38355322

; TIMING_CFG_2
WM32	0xe000210C 0x039048c7

; DDR_SDRAM_MODE
WM32	0xe0002118 0x00000432

; DDR_SDRAM_INTERVAL
WM32	0xe0002124 0x05150100

; DDR_SDRAM_CFG2
WM32	0xe0002114 0x24000000

; DDR_SDRAM_CLK_CNTL
WM32	0xe0002130 0x03000000

DELAY 200

; enable the memory interface
; DDR_SDRAM_CFG
; enable the memory interface
WM32	0xe0002110 0xc3000000

;================= end flash programming =====================
;


[TARGET]
CPUTYPE     8548        ;the CPU type
JTAGCLOCK   0           ;use 16 MHz JTAG clock
;STARTUP     STOP 5000   ;let U-boot code setup the system
STARTUP     HALT        ;halt core while HRESET is asserted
BREAKMODE   HARD      	;SOFT or HARD, HARD uses PPC hardware breakpoint
STEPMODE    HWBP        ;JTAG or HWBP, HWBP uses a hardware breakpoint
WAKEUP      500         ;give reset time to complete
POWERUP     5000        ;start delay after power-up detected in ms

[REGS]
FILE        $reg8548.def


[HOST]
IP          10.101.43.10
FILE        vmlinux.8548
FORMAT      ELF
LOAD        MANUAL      ;load code MANUAL or AUTO after reset
DUMP        e500.bin
PROMPT      atum>

[FLASH]
CHIPTYPE    MIRRORX16   ;S29GL01GP
CHIPSIZE    0x8000000    ;The size of one flash chip in bytes - 1Gb
BUSWIDTH    16          ;The width of the flash memory bus in bits (8 | 16 | 32)
FILE        u-boot.bin
FORMAT      BIN 0xF8000000
ERASE       0xF8000000          ;erase sector 0

[REGS]
FILE        $reg8548.def