[U-Boot-Users] minimum bdi config to read flash on 85xx

[robert lazarski]

On 9/4/07, Ben Warren <bwarren at qstreams.com> wrote:
> David Hawkins wrote:
> > Hi Robert,
> >
> >
> >> The big problem we have now: is this a hardware issue or a bdi config
> >> issue? Aside from the flash we have 1GigaByte of DDR ram. Can anyone
> >> help us track our flash issues down to be hardware, config file, or
> >> some combination? The hardware guys think the board is fine.
> >>
> >
> > Have you checked that the Flash is getting accessed?
> >
> Very good point. I know you've made many changes since your initial
> setup Robert. Did any of them make the chip select strobe?

We now see the CE on the flash chip going from 3.3v to 0 on reset of
the 8548. We also see the same behavior when issuing a mdh command on
the bdi - however, we cannot see any activity whatsoever on the Ax
pins on the spansion flash chip when trying read via the bdi and mdh.

Getting deep into 8548, the "pin strapping" I believe is controlled by
the POR Boot Mode Status Register (PORBMSR) in "20.4.1.2" in:

http://www.freescale.com/files/32bit/doc/ref_manual/MPC8548ERM.pdf

Reading the register PORBMSR we get: 0x86370000 which I'm reading as:

1 0000 110 00 11 0 11 100 00000000000000

0         BCFG = 1 The CPU is allowed to start fetching boot code.
1-4      reserved
5-7      ROM_LOC = 110 Local bus GPCM:16-bit (our local bus is 16bit)
8-9      reserved
10-11   BSCFG = 11 Boot sequencer disabled
12       reserved
13-15   Host/agent = PCI1/PCI-X and Serial RapidIO agent mode
16-31   reserved.

Our flash is 128MB and we think we set the LAW correctly in the bdi
config file as F8000000 .  In 4.3.1.3 however, it defaults to FF80000
and says:

 "If translation is to be performed to a page outside the default boot
ROM address range defined in the MPC8548E (8 Mbytes at 0x0_FF80_0000
to 0x0_FFFF_FFFF as defined in Section 4.4.3.3, "Boot ROM Location"),
the external host or boot sequencer must then also set up a local
access window to define the routing of the boot code fetch to the
target interface that contains the boot code, because the BPTR defines
only the address
translation, not the target interface."

Perhaps we're not doing that right?

> > I'm working with an 83xx based board, so the 85xx will
> > be slightly different, but here's what I'd look for.
> > When the processor boots, it reads a hardware configuration
> > word (HCW) that tells it where to boot from. The pin strapping
> > can be set to tell it to use Flash. Assuming the HCW
> > is read correctly, you should be able to see the
> > CE# line on the Flash assert when the processor boots.
> >
> >
> Also, on the 83xx you can set the RCW values directly from the BDI-2000,
> using an entry like the following in the TARGET section:
>
> RCW 0x8060a000 0x04230000

I did see RCW while googling, but that appears not to be present on
the 85xx as I couldn't find it in the 85xx bdi manual or the freescale
manual. Anyone know the equivalent?

Thanks all!
Robert