[U-Boot-Users] [PATCH 3/3] Apollon BSP support
Kyungmin Park
kmpark at infradead.org
Fri Sep 14 02:52:21 CEST 2007
Apollon BSP support
The Apollon based on OMAP2420 is designed for OneNAND development.
It's similar with OMAP2420 H4 except some peripherals.
Now this board is maintained at mainline kernel.
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
diff --git a/board/apollon/mem.c b/board/apollon/mem.c
new file mode 100644
index 0000000..a4980b0
--- /dev/null
+++ b/board/apollon/mem.c
@@ -0,0 +1,229 @@
+/*
+ * (C) Copyright 2005-2007
+ * Samsung Electronics,
+ * Kyungmin Park <kyungmin.park at samsung.com>
+ *
+ * Derived from omap2420
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/omap2420.h>
+#include <asm/io.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/clocks.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/sys_info.h>
+
+#include "mem.h"
+
+/************************************************************
+ * sdelay() - simple spin loop. Will be constant time as
+ * its generally used in 12MHz bypass conditions only. This
+ * is necessary until timers are accessible.
+ *
+ * not inline to increase chances its in cache when called
+ *************************************************************/
+void sdelay(unsigned long loops)
+{
+ __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
+ "bne 1b":"=r" (loops):"0"(loops));
+}
+
+/*********************************************************************************
+ * prcm_init() - inits clocks for PRCM as defined in clocks.h (config II default).
+ * -- called from SRAM, or Flash (using temp SRAM stack).
+ *********************************************************************************/
+void prcm_init(void)
+{
+}
+
+/**************************************************************************
+ * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow
+ * command line mem=xyz use all memory with out discontigious support
+ * compiled in. Could do it at the ATAG, but there really is two banks...
+ * Called as part of 2nd phase DDR init.
+ **************************************************************************/
+void make_cs1_contiguous(void)
+{
+ u32 size, a_add_low, a_add_high;
+
+ size = get_sdr_cs_size(SDRC_CS0_OSET);
+ size /= SZ_32M; /* find size to offset CS1 */
+ a_add_high = (size & 3) << 8; /* set up low field */
+ a_add_low = (size & 0x3C) >> 2; /* set up high field */
+ __raw_writel((a_add_high | a_add_low), SDRC_CS_CFG);
+
+}
+
+/********************************************************
+ * mem_ok() - test used to see if timings are correct
+ * for a part. Helps in gussing which part
+ * we are currently using.
+ *******************************************************/
+u32 mem_ok(void)
+{
+ u32 val1, val2;
+ u32 pattern = 0x12345678;
+
+ __raw_writel(0x0, OMAP2420_SDRC_CS0 + 0x400); /* clear pos A */
+ __raw_writel(pattern, OMAP2420_SDRC_CS0); /* pattern to pos B */
+ __raw_writel(0x0, OMAP2420_SDRC_CS0 + 4); /* remove pattern off the bus */
+ val1 = __raw_readl(OMAP2420_SDRC_CS0 + 0x400); /* get pos A value */
+ val2 = __raw_readl(OMAP2420_SDRC_CS0); /* get val2 */
+
+ if ((val1 != 0) || (val2 != pattern)) /* see if pos A value changed */
+ return (0);
+ else
+ return (1);
+}
+
+/********************************************************
+ * sdrc_init() - init the sdrc chip selects CS0 and CS1
+ * - early init routines, called from flash or
+ * SRAM.
+ *******************************************************/
+void sdrc_init(void)
+{
+#define EARLY_INIT 1
+ /* only init up first bank here */
+ do_sdrc_init(SDRC_CS0_OSET, EARLY_INIT);
+}
+
+/*************************************************************************
+ * do_sdrc_init(): initialize the SDRAM for use.
+ * -called from low level code with stack only.
+ * -code sets up SDRAM timing and muxing for 2422 or 2420.
+ * -optimal settings can be placed here, or redone after i2c
+ * inspection of board info
+ *
+ * This is a bit ugly, but should handle all memory moduels
+ * used with the APOLLON. The first time though this code from s_init()
+ * we configure the first chip select. Later on we come back and
+ * will configure the 2nd chip select if it exists.
+ *
+ **************************************************************************/
+void do_sdrc_init(u32 offset, u32 early)
+{
+}
+
+/*****************************************************
+ * gpmc_init(): init gpmc bus
+ * Init GPMC for x16, MuxMode (SDRAM in x32).
+ * This code can only be executed from SRAM or SDRAM.
+ *****************************************************/
+void gpmc_init(void)
+{
+ u32 mux = 0, mtype, mwidth, rev, tval;
+
+ rev = get_cpu_rev();
+ if (rev == CPU_2420_2422_ES1)
+ tval = 1;
+ else
+ tval = 0; /* disable bit switched meaning */
+
+ /* global settings */
+ __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */
+ __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */
+ __raw_writel(tval, GPMC_TIMEOUT_CONTROL); /* timeout disable */
+#ifdef CFG_NAND_BOOT
+ __raw_writel(0x001, GPMC_CONFIG); /* set nWP, disable limited addr */
+#else
+ __raw_writel(0x111, GPMC_CONFIG); /* set nWP, disable limited addr */
+#endif
+
+ /* discover bus connection from sysboot */
+ if (is_gpmc_muxed() == GPMC_MUXED)
+ mux = BIT9;
+ mtype = get_gpmc0_type();
+ mwidth = get_gpmc0_width();
+
+ /* setup cs0 */
+ __raw_writel(0x0, GPMC_CONFIG7_0); /* disable current map */
+ sdelay(1000);
+
+#ifdef CFG_NOR_BOOT
+ __raw_writel(APOLLON_24XX_GPMC_CONFIG1_3, GPMC_CONFIG1_0);
+ __raw_writel(APOLLON_24XX_GPMC_CONFIG2_3, GPMC_CONFIG2_0);
+ __raw_writel(APOLLON_24XX_GPMC_CONFIG3_3, GPMC_CONFIG3_0);
+ __raw_writel(APOLLON_24XX_GPMC_CONFIG4_3, GPMC_CONFIG4_0);
+ __raw_writel(APOLLON_24XX_GPMC_CONFIG5_3, GPMC_CONFIG5_0);
+ __raw_writel(APOLLON_24XX_GPMC_CONFIG6_3, GPMC_CONFIG6_0);
+ __raw_writel(APOLLON_24XX_GPMC_CONFIG7_3, GPMC_CONFIG7_0);
+#else
+ __raw_writel(APOLLON_24XX_GPMC_CONFIG1_0 | mux | mtype | mwidth,
+ GPMC_CONFIG1_0);
+ __raw_writel(APOLLON_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_0);
+ __raw_writel(APOLLON_24XX_GPMC_CONFIG3_0, GPMC_CONFIG3_0);
+ __raw_writel(APOLLON_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_0);
+ __raw_writel(APOLLON_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_0);
+ __raw_writel(APOLLON_24XX_GPMC_CONFIG6_0, GPMC_CONFIG6_0);
+ __raw_writel(APOLLON_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_0); /* enable new mapping */
+#endif
+ sdelay(2000);
+
+ /* setup cs1 */
+ __raw_writel(0, GPMC_CONFIG7_1); /* disable any mapping */
+ sdelay(1000);
+
+ __raw_writel(APOLLON_24XX_GPMC_CONFIG1_1, GPMC_CONFIG1_1);
+ __raw_writel(APOLLON_24XX_GPMC_CONFIG2_1, GPMC_CONFIG2_1);
+ __raw_writel(APOLLON_24XX_GPMC_CONFIG3_1, GPMC_CONFIG3_1);
+ __raw_writel(APOLLON_24XX_GPMC_CONFIG4_1, GPMC_CONFIG4_1);
+ __raw_writel(APOLLON_24XX_GPMC_CONFIG5_1, GPMC_CONFIG5_1);
+ __raw_writel(APOLLON_24XX_GPMC_CONFIG6_1, GPMC_CONFIG6_1);
+ __raw_writel(APOLLON_24XX_GPMC_CONFIG7_1, GPMC_CONFIG7_1);
+ sdelay(2000);
+
+ /* setup cs2 */
+ __raw_writel(APOLLON_24XX_GPMC_CONFIG1_0 | mux | mtype | mwidth,
+ GPMC_CONFIG1_2);
+ /* It's same as cs 0 */
+ __raw_writel(APOLLON_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_2);
+ __raw_writel(APOLLON_24XX_GPMC_CONFIG3_0, GPMC_CONFIG3_2);
+ __raw_writel(APOLLON_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_2);
+ __raw_writel(APOLLON_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_2);
+ __raw_writel(APOLLON_24XX_GPMC_CONFIG6_0, GPMC_CONFIG6_2);
+#ifdef CFG_NOR_BOOT
+ __raw_writel(APOLLON_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_2);
+#else
+ __raw_writel(APOLLON_24XX_GPMC_CONFIG7_2, GPMC_CONFIG7_2);
+#endif
+
+#ifndef CFG_NOR_BOOT
+ /* setup cs3 */
+ __raw_writel(0, GPMC_CONFIG7_3); /* disable any mapping */
+ sdelay(1000);
+
+ __raw_writel(APOLLON_24XX_GPMC_CONFIG1_3, GPMC_CONFIG1_3);
+ __raw_writel(APOLLON_24XX_GPMC_CONFIG2_3, GPMC_CONFIG2_3);
+ __raw_writel(APOLLON_24XX_GPMC_CONFIG3_3, GPMC_CONFIG3_3);
+ __raw_writel(APOLLON_24XX_GPMC_CONFIG4_3, GPMC_CONFIG4_3);
+ __raw_writel(APOLLON_24XX_GPMC_CONFIG5_3, GPMC_CONFIG5_3);
+ __raw_writel(APOLLON_24XX_GPMC_CONFIG6_3, GPMC_CONFIG6_3);
+ __raw_writel(APOLLON_24XX_GPMC_CONFIG7_3, GPMC_CONFIG7_3);
+#endif
+
+#ifndef ASYNC_NOR
+ __raw_writew(0xaa, (APOLLON_CS3_BASE + 0xaaa));
+ __raw_writew(0x55, (APOLLON_CS3_BASE + 0x554));
+ __raw_writew(0xc0, (APOLLON_CS3_BASE | SYNC_NOR_VALUE));
+#endif
+ sdelay(2000);
+}
diff --git a/board/apollon/mem.h b/board/apollon/mem.h
new file mode 100644
index 0000000..aed7e1d
--- /dev/null
+++ b/board/apollon/mem.h
@@ -0,0 +1,170 @@
+/*
+ * (C) Copyright 2005-2007
+ * Samsung Electronics,
+ * Kyungmin Park <kyungmin.park at samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _APOLLON_OMAP24XX_MEM_H_
+#define _APOLLON_OMAP24XX_MEM_H_
+
+/* Slower full frequency range default timings for x32 operation*/
+#define APOLLON_2420_SDRC_SHARING 0x00000100
+#define APOLLON_2420_SDRC_MDCFG_0_DDR 0x00d04011
+#define APOLLON_2420_SDRC_MR_0_DDR 0x00000032
+
+/* optimized timings good for current shipping parts */
+#define APOLLON_242X_SDRC_ACTIM_CTRLA_0_100MHz 0x4A59B485
+#define APOLLON_242X_SDRC_ACTIM_CTRLB_0_100MHz 0x0000000C
+
+#define APOLLON_242X_SDRC_ACTIM_CTRLA_0_166MHz 0x7BA35907
+#define APOLLON_242X_SDRC_ACTIM_CTRLB_0_166MHz 0x00000013
+
+#define APOLLON_242X_SDRC_RFR_CTRL_100MHz 0x00030001
+#define APOLLON_242X_SDRC_RFR_CTRL_166MHz 0x00044C01
+
+#define APOLLON_242x_SDRC_DLLAB_CTRL_100MHz 0x00007306
+#define APOLLON_242x_SDRC_DLLAB_CTRL_166MHz 0x00000506
+
+#ifdef PRCM_CONFIG_I
+# define APOLLON_2420_SDRC_ACTIM_CTRLA_0 APOLLON_242X_SDRC_ACTIM_CTRLA_0_166MHz
+# define APOLLON_2420_SDRC_ACTIM_CTRLB_0 APOLLON_242X_SDRC_ACTIM_CTRLB_0_166MHz
+# define APOLLON_2420_SDRC_RFR_CTRL APOLLON_242X_SDRC_RFR_CTRL_166MHz
+# define APOLLON_2420_SDRC_DLLAB_CTRL APOLLON_242x_SDRC_DLLAB_CTRL_166MHz
+#elif PRCM_CONFIG_II
+# define APOLLON_2420_SDRC_ACTIM_CTRLA_0 APOLLON_242X_SDRC_ACTIM_CTRLA_0_100MHz
+# define APOLLON_2420_SDRC_ACTIM_CTRLB_0 APOLLON_242X_SDRC_ACTIM_CTRLB_0_100MHz
+# define APOLLON_2420_SDRC_RFR_CTRL APOLLON_242X_SDRC_RFR_CTRL_100MHz
+# define APOLLON_2420_SDRC_DLLAB_CTRL APOLLON_242x_SDRC_DLLAB_CTRL_100MHz
+#endif
+
+/* GPMC settings */
+#ifdef PRCM_CONFIG_I /* L3 at 165MHz */
+/* CS0: OneNAND */
+# define APOLLON_24XX_GPMC_CONFIG1_0 0x00000001
+# define APOLLON_24XX_GPMC_CONFIG2_0 0x000c1000
+# define APOLLON_24XX_GPMC_CONFIG3_0 0x00030400
+# define APOLLON_24XX_GPMC_CONFIG4_0 0x0b841006
+# define APOLLON_24XX_GPMC_CONFIG5_0 0x020f0c11
+# define APOLLON_24XX_GPMC_CONFIG6_0 0x00000000
+# define APOLLON_24XX_GPMC_CONFIG7_0 (0x00000e40|(APOLLON_CS0_BASE >> 24))
+
+/* CS1: Ethernet */
+# define APOLLON_24XX_GPMC_CONFIG1_1 0x00011200
+# define APOLLON_24XX_GPMC_CONFIG2_1 0x001F1F01
+# define APOLLON_24XX_GPMC_CONFIG3_1 0x00080803
+# define APOLLON_24XX_GPMC_CONFIG4_1 0x1C0b1C0a
+# define APOLLON_24XX_GPMC_CONFIG5_1 0x041F1F1F
+# define APOLLON_24XX_GPMC_CONFIG6_1 0x000004C4
+# define APOLLON_24XX_GPMC_CONFIG7_1 (0x00000F40|(APOLLON_CS1_BASE >> 24))
+
+/* CS2: OneNAND */
+/* It's same as CS0 */
+# define APOLLON_24XX_GPMC_CONFIG7_2 (0x00000e40|(APOLLON_CS2_BASE >> 24))
+
+/* CS3: NOR */
+#ifdef ASYNC_NOR
+# define APOLLON_24XX_GPMC_CONFIG1_3 0x00021201
+# define APOLLON_24XX_GPMC_CONFIG2_3 0x00121601
+# define APOLLON_24XX_GPMC_CONFIG3_3 0x00040401
+# define APOLLON_24XX_GPMC_CONFIG4_3 0x12061605
+# define APOLLON_24XX_GPMC_CONFIG5_3 0x01151317
+#else
+# define SYNC_NOR_VALUE 0x24aaa
+# define APOLLON_24XX_GPMC_CONFIG1_3 0xe5011211
+# define APOLLON_24XX_GPMC_CONFIG2_3 0x00090b01
+# define APOLLON_24XX_GPMC_CONFIG3_3 0x00020201
+# define APOLLON_24XX_GPMC_CONFIG4_3 0x09030b03
+# define APOLLON_24XX_GPMC_CONFIG5_3 0x010a0a0c
+#endif /* ASYNC_NOR */
+# define APOLLON_24XX_GPMC_CONFIG6_3 0x00000000
+# define APOLLON_24XX_GPMC_CONFIG7_3 (0x00000e40|(APOLLON_CS3_BASE >> 24))
+#endif /* endif PRCM_CONFIG_I */
+
+#ifdef PRCM_CONFIG_II /* L3 at 100MHz */
+/* CS0: OneNAND */
+# define APOLLON_24XX_GPMC_CONFIG1_0 0x00000001
+# define APOLLON_24XX_GPMC_CONFIG2_0 0x00081080
+# define APOLLON_24XX_GPMC_CONFIG3_0 0x00030300
+# define APOLLON_24XX_GPMC_CONFIG4_0 0x08041004
+# define APOLLON_24XX_GPMC_CONFIG5_0 0x020b0910
+# define APOLLON_24XX_GPMC_CONFIG6_0 0x00000000
+# define APOLLON_24XX_GPMC_CONFIG7_0 (0x00000C40|(APOLLON_CS0_BASE >> 24))
+
+/* CS1: ethernet */
+# define APOLLON_24XX_GPMC_CONFIG1_1 0x00401203
+# define APOLLON_24XX_GPMC_CONFIG2_1 0x001F1F01
+# define APOLLON_24XX_GPMC_CONFIG3_1 0x00080803
+# define APOLLON_24XX_GPMC_CONFIG4_1 0x1C091C09
+# define APOLLON_24XX_GPMC_CONFIG5_1 0x041F1F1F
+# define APOLLON_24XX_GPMC_CONFIG6_1 0x000004C4
+# define APOLLON_24XX_GPMC_CONFIG7_1 (0x00000F40|(APOLLON_CS1_BASE >> 24))
+
+/* CS2: OneNAND */
+/* It's same as CS0 */
+# define APOLLON_24XX_GPMC_CONFIG7_2 (0x00000e40|(APOLLON_CS2_BASE >> 24))
+
+/* CS3: NOR */
+#define ASYNC_NOR
+#ifdef ASYNC_NOR
+# define APOLLON_24XX_GPMC_CONFIG1_3 0x00021201
+# define APOLLON_24XX_GPMC_CONFIG2_3 0x00121601
+# define APOLLON_24XX_GPMC_CONFIG3_3 0x00040401
+# define APOLLON_24XX_GPMC_CONFIG4_3 0x12061605
+# define APOLLON_24XX_GPMC_CONFIG5_3 0x01151317
+#else
+# define SYNC_NOR_VALUE 0x24aaa
+# define APOLLON_24XX_GPMC_CONFIG1_3 0xe1001202
+# define APOLLON_24XX_GPMC_CONFIG2_3 0x00151501
+# define APOLLON_24XX_GPMC_CONFIG3_3 0x00050501
+# define APOLLON_24XX_GPMC_CONFIG4_3 0x0e070e07
+# define APOLLON_24XX_GPMC_CONFIG5_3 0x01131F1F
+#endif /* ASYNC_NOR */
+# define APOLLON_24XX_GPMC_CONFIG6_3 0x00000000
+# define APOLLON_24XX_GPMC_CONFIG7_3 (0x00000C40|(APOLLON_CS3_BASE >> 24))
+#endif /* endif PRCM_CONFIG_II */
+
+#ifdef PRCM_CONFIG_III /* L3 at 133MHz */
+# ifdef CFG_NAND_BOOT
+# define APOLLON_24XX_GPMC_CONFIG1_0 0x0
+# define APOLLON_24XX_GPMC_CONFIG2_0 0x00141400
+# define APOLLON_24XX_GPMC_CONFIG3_0 0x00141400
+# define APOLLON_24XX_GPMC_CONFIG4_0 0x0F010F01
+# define APOLLON_24XX_GPMC_CONFIG5_0 0x010C1414
+# define APOLLON_24XX_GPMC_CONFIG6_0 0x00000A80
+# else /* NOR boot */
+# define APOLLON_24XX_GPMC_CONFIG1_0 0x3
+# define APOLLON_24XX_GPMC_CONFIG2_0 0x00151501
+# define APOLLON_24XX_GPMC_CONFIG3_0 0x00060602
+# define APOLLON_24XX_GPMC_CONFIG4_0 0x10081008
+# define APOLLON_24XX_GPMC_CONFIG5_0 0x01131F1F
+# define APOLLON_24XX_GPMC_CONFIG6_0 0x000004c4
+# endif /* endif CFG_NAND_BOOT */
+# define APOLLON_24XX_GPMC_CONFIG7_0 (0x00000C40|(APOLLON_CS0_BASE >> 24))
+# define APOLLON_24XX_GPMC_CONFIG1_1 0x00011000
+# define APOLLON_24XX_GPMC_CONFIG2_1 0x001f1f01
+# define APOLLON_24XX_GPMC_CONFIG3_1 0x00080803
+# define APOLLON_24XX_GPMC_CONFIG4_1 0x1C091C09
+# define APOLLON_24XX_GPMC_CONFIG5_1 0x041f1F1F
+# define APOLLON_24XX_GPMC_CONFIG6_1 0x000004C4
+# define APOLLON_24XX_GPMC_CONFIG7_1 (0x00000F40|(APOLLON_CS1_BASE >> 24))
+#endif /* endif CFG_PRCM_III */
+
+#endif /* endif _APOLLON_OMAP24XX_MEM_H_ */
diff --git a/include/asm-arm/arch-arm1136/mux.h b/include/asm-arm/arch-arm1136/mux.h
index 67c8419..8bcd7a3 100644
--- a/include/asm-arm/arch-arm1136/mux.h
+++ b/include/asm-arm/arch-arm1136/mux.h
@@ -28,6 +28,7 @@ typedef unsigned int uint32;
void muxSetupSDRC(void);
void muxSetupGPMC(void);
void muxSetupUsb0(void);
+void muxSetupUsbHost(void);
void muxSetupUart3(void);
void muxSetupI2C1(void);
void muxSetupUART1(void);
@@ -70,6 +71,7 @@ void muxSetupHDQ(void);
#define CONTROL_PADCONF_SPI1_SIMO ((volatile unsigned char *)0x48000100)
#define CONTROL_PADCONF_SPI1_SOMI ((volatile unsigned char *)0x48000101)
#define CONTROL_PADCONF_SPI1_NCS0 ((volatile unsigned char *)0x48000102)
+#define CONTROL_PADCONF_SPI1_NCS1 ((volatile unsigned char *)0x48000103)
#define CONTROL_PADCONF_MCBSP1_FSR ((volatile unsigned char *)0x4800010B)
diff --git a/include/asm-arm/arch-arm1136/omap2420.h b/include/asm-arm/arch-arm1136/omap2420.h
index d833035..0c11bec 100644
--- a/include/asm-arm/arch-arm1136/omap2420.h
+++ b/include/asm-arm/arch-arm1136/omap2420.h
@@ -77,6 +77,20 @@
#define GPMC_CONFIG5_1 (OMAP2420_GPMC_BASE+0xA0)
#define GPMC_CONFIG6_1 (OMAP2420_GPMC_BASE+0xA4)
#define GPMC_CONFIG7_1 (OMAP2420_GPMC_BASE+0xA8)
+#define GPMC_CONFIG1_2 (OMAP2420_GPMC_BASE+0xC0)
+#define GPMC_CONFIG2_2 (OMAP2420_GPMC_BASE+0xC4)
+#define GPMC_CONFIG3_2 (OMAP2420_GPMC_BASE+0xC8)
+#define GPMC_CONFIG4_2 (OMAP2420_GPMC_BASE+0xCC)
+#define GPMC_CONFIG5_2 (OMAP2420_GPMC_BASE+0xD0)
+#define GPMC_CONFIG6_2 (OMAP2420_GPMC_BASE+0xD4)
+#define GPMC_CONFIG7_2 (OMAP2420_GPMC_BASE+0xD8)
+#define GPMC_CONFIG1_3 (OMAP2420_GPMC_BASE+0xF0)
+#define GPMC_CONFIG2_3 (OMAP2420_GPMC_BASE+0xF4)
+#define GPMC_CONFIG3_3 (OMAP2420_GPMC_BASE+0xF8)
+#define GPMC_CONFIG4_3 (OMAP2420_GPMC_BASE+0xFC)
+#define GPMC_CONFIG5_3 (OMAP2420_GPMC_BASE+0x100)
+#define GPMC_CONFIG6_3 (OMAP2420_GPMC_BASE+0x104)
+#define GPMC_CONFIG7_3 (OMAP2420_GPMC_BASE+0x108)
/* SMS */
#define OMAP2420_SMS_BASE 0x68008000
@@ -209,13 +223,24 @@
#define SRAM_OFFSET2 0x0000F800
#define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2)
-#define LOW_LEVEL_SRAM_STACK 0x4020FFFC
-
-#define PERIFERAL_PORT_BASE 0x480FE003
-
/* FPGA on Debug board.*/
#define ETH_CONTROL_REG (H4_CS1_BASE+0x30b)
#define LAN_RESET_REGISTER (H4_CS1_BASE+0x1c)
#endif /* endif CONFIG_2420H4 */
+#if defined(CONFIG_APOLLON)
+#define APOLLON_CS0_BASE 0x00000000 /* OneNAND */
+#define APOLLON_CS1_BASE 0x08000000 /* ethernet */
+#define APOLLON_CS2_BASE 0x10000000 /* OneNAND */
+#define APOLLON_CS3_BASE 0x18000000 /* NOR */
+
+#define ETH_CONTROL_REG (APOLLON_CS1_BASE + 0x30b)
+#define LAN_RESET_REGISTER (APOLLON_CS1_BASE + 0x1c)
+#endif /* endif CONFIG_APOLLON */
+
+/* Common */
+#define LOW_LEVEL_SRAM_STACK 0x4020FFFC
+
+#define PERIFERAL_PORT_BASE 0x480FE003
+
#endif
diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h
index f6a5b4f..ab19047 100644
--- a/include/asm-arm/mach-types.h
+++ b/include/asm-arm/mach-types.h
@@ -737,6 +737,7 @@ extern unsigned int __machine_arch_type;
#define MACH_TYPE_CB3RUFC 726
#define MACH_TYPE_MP2USB 727
#define MACH_TYPE_AT91SAM9261EK 848
+#define MACH_TYPE_OMAP_APOLLON 919
#define MACH_TYPE_PDNB3 1002
#define MACH_TYPE_AT91SAM9260EK 1099
#define MACH_TYPE_AT91RM9200DF 1119
@@ -6826,6 +6827,18 @@ extern unsigned int __machine_arch_type;
# define machine_is_omap_h4() (0)
#endif
+#ifdef CONFIG_MACH_OMAP_APOLLON
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_OMAP_APOLLON
+# endif
+# define machine_is_omap_apollon() (machine_arch_type == MACH_TYPE_OMAP_APOLLON)
+#else
+# define machine_is_omap_apollon() (0)
+#endif
+
#ifdef CONFIG_MACH_N10
# ifdef machine_arch_type
# undef machine_arch_type
diff --git a/include/configs/apollon.h b/include/configs/apollon.h
new file mode 100644
index 0000000..7c8d447
--- /dev/null
+++ b/include/configs/apollon.h
@@ -0,0 +1,239 @@
+/*
+ * (C) Copyright 2005-2007
+ * Samsung Electronics,
+ * Kyungmin Park <kyungmin.park at samsung.com>
+ *
+ * Configuration settings for the 2420 Samsung Apollon board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
+#define CONFIG_OMAP 1 /* in a TI OMAP core */
+#define CONFIG_OMAP2420 1 /* which is in a 2420 */
+#define CONFIG_OMAP2420_APOLLON 1
+#define CONFIG_APOLLON 1
+#define CONFIG_APOLLON_PLUS 1 /* If you have apollon plus 1.x */
+
+/* Clock config to target*/
+#define PRCM_CONFIG_I 1
+//#define PRCM_CONFIG_II 1
+
+/* Boot method */
+/* uncomment if you use NOR boot */
+//#define CFG_NOR_BOOT 1
+
+/* uncommnet if you use NOR on CS3 */
+//#define CFG_USE_NOR 1
+
+#ifdef CFG_NOR_BOOT
+#undef CFG_USE_NOR
+#define CFG_USE_NOR 1
+#endif
+
+#include <asm/arch/omap2420.h> /* get chip and board defs */
+
+#define V_SCLK 12000000
+
+/* input clock of PLL */
+/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */
+#define CONFIG_SYS_CLK_FREQ V_SCLK
+
+#undef CONFIG_USE_IRQ /* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+#define CONFIG_REVISION_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_ENV_SIZE SZ_128K /* Total Size of Environment Sector */
+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + SZ_128K)
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * SMC91c96 Etherent
+ */
+#define CONFIG_DRIVER_LAN91C96
+#define CONFIG_LAN91C96_BASE (APOLLON_CS1_BASE+0x300)
+#define CONFIG_LAN91C96_EXT_PHY
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK (48000000) /* 48MHz (APLL96/2) */
+
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE (-4)
+#define CFG_NS16550_CLK V_NS16550_CLK /* 3MHz (1.5MHz*2) */
+#define CFG_NS16550_COM1 OMAP2420_UART1
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL1 1 /* UART1 on H4 */
+
+ /*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C
+#define CFG_I2C_SPEED 100000
+#define CFG_I2C_SLAVE 1
+#define CONFIG_DRIVER_OMAP24XX_I2C
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CFG_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_ONENAND
+
+#undef CONFIG_CMD_AUTOSCRIPT
+
+#ifndef CFG_USE_NOR
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#endif
+
+#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
+
+#define CONFIG_BOOTDELAY 1
+
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 192.168.116.25
+#define CONFIG_SERVERIP 192.168.116.1
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_ETHADDR 00:0E:99:00:24:20
+
+#ifdef CONFIG_APOLLON_PLUS
+#define CONFIG_BOOTARGS "root=/dev/nfs rw mem=64M console=ttyS0,115200n8 ip=192.168.116.25:192.168.116.1:192.168.116.1:255.255.255.0:apollon:eth0:off nfsroot=/tftpboot/nfsroot profile=2"
+#else
+#define CONFIG_BOOTARGS "root=/dev/nfs rw mem=128M console=ttyS0,115200n8 ip=192.168.116.25:192.168.116.1:192.168.116.1:255.255.255.0:apollon:eth0:off nfsroot=/tftpboot/nfsroot profile=2"
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "Image=tftp 0x80008000 Image\; go 0x80008000\0" \
+ "zImage=tftp 0x80180000 zImage\; go 0x80180000\0" \
+ "uImage=tftp 0x80180000 uImage\; bootm 0x80180000\0" \
+ "uboot=tftp 0x80008000 u-boot.bin\; go 0x80008000\0" \
+ "xloader=tftp 0x80180000 x-load.bin\; cp.w 0x80180000 0x00000400 0x1000\; go 0x00000400\0" \
+ "syncmode50=mw.w 0x1e442 0xc0c4\; mw 0x6800a060 0xe30d1201\0" \
+ "syncmode=mw.w 0x1e442 0xe0f4\; mw 0x6800a060 0xe30d1201\0" \
+ "norboot=cp32 0x18040000 0x80008000 0x200000\; go 0x80008000\0" \
+ "oneboot=onenand read 0x80008000 0x40000 0x200000\; go 0x80008000\0"\
+ "onesyncboot=run syncmode oneboot\0" \
+ "bootcmd=run uboot\0"
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define V_PROMPT "Apollon # "
+
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT V_PROMPT
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START (OMAP2420_SDRC_CS0) /* memtest works on */
+#define CFG_MEMTEST_END (OMAP2420_SDRC_CS0+SZ_31M)
+
+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR (OMAP2420_SDRC_CS0) /* default load address */
+
+/* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
+ * 32KHz clk, or from external sig. This rate is divided by a local divisor.
+ */
+#define V_PVT 7 /* use with 12MHz/128 */
+
+#define CFG_TIMERBASE OMAP2420_GPT2
+#define CFG_PVT V_PVT /* 2^(pvt+1) */
+#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE SZ_128K /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* CS1 may or may not be populated */
+#define PHYS_SDRAM_1 OMAP2420_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE SZ_128M
+#define PHYS_SDRAM_2 OMAP2420_SDRC_CS1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#ifdef CFG_USE_NOR
+/* OneNAND boot, NOR has CS3, But NOR has CS0 when NOR boot */
+#define CFG_FLASH_BASE 0x18000000
+#define CFG_MAX_FLASH_BANKS 1
+#define CFG_MAX_FLASH_SECT 1024
+/*-----------------------------------------------------------------------
+
+ * CFI FLASH driver setup
+ */
+#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
+//#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */
+#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */
+
+#else /* !CFG_USE_NOR */
+
+#define CFG_NO_FLASH 1
+#endif /* CFG_USE_NOR */
+
+/* OneNAND boot, OneNAND has CS0, NOR boot ONeNAND has CS2 */
+#define CFG_ONENAND_BASE 0x00000000
+#define CFG_ENV_IS_IN_ONENAND 1
+#define CFG_ENV_ADDR 0x00020000
+
+#endif /* __CONFIG_H */
More information about the U-Boot
mailing list