[U-Boot-Users] [PATCH] Add Vitesse 8601 support to TSEC driver

[Andre Schwarz]

Andy Fleming schrieb:
> On Tue, Apr 1, 2008 at 9:08 AM, Andre Schwarz
> <andre.schwarz at matrix-vision.de> wrote:
>   
>>  Tor,
>>
>>  after investigating the tsec code I'm wondering how your PHY works in
>>  RGMII mode ...
>>
>>  I think that there are some things missing, e.g. taking RGMII into
>>  account during tsec_init.
>>
>>  /* Init ECNTRL */
>>  regs->ecntrl = ECNTRL_INIT_SETTINGS;
>>
>>  If you look carefully, you'll notice that ecntrl's RPM bit is
>> read-only. Those bits are configured by POR pin strappings.
>>
>>
>>  sorry, my documentation (MPC8349EARM rev.1) declares this register
>> read-write.
>>  Of course it will be configured by the HRCW but can be overwritten
>> afterwards.
>>
>>  If this is not true it's a documentation bug.
>>     
>
>
> Thank you for bringing this to my attention.  It is almost certainly a
> bug.  If you look at the 8349ERM (rather than the 8349EARM), you'll
> see that the bits are read-only (except for R100, which tsec.c does
> modify based on the link type).  I will file a bug with the docs
> people.
>
>
>   
I've x-checked and printed the register after init.
You're right - it's read only and the RPM bit is set.
But the ECNTL  register description @ 15.5.3.1.4 says "read/write" to 
all bits ...
>>  You may be more familiar with the UEC, which doesn't automatically
>> detect the link type, but is otherwise fairly similar to the tsec.
>>
>>
>>  What do you mean ?
>>  I'm trying to get two VSC8601 RGMII PHYs running on a MPC8343B ...
>>     
>
> sorry, I forgot which ethernet controller you were using, and I'm not
> as familiar with the 83xx family as the 85xx family.  Some of our
> parts have the QUICC Engine, which has an ethernet controller with
> some similar registers to the TSEC's.  I was guessing that was why you
> thought those bits were writable, rather than a documentation bug, but
> clearly I was wrong.  :)
>
>   
no problem.

Andre
> Andy
>
> Andy
>   



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