[U-Boot-Users] [PATCH] ppc4xx: Fix crash on sequoia with cache enabled

[Anatolij Gustschin]

Currently U-Boot crashes on sequoia board in CPU POST if
cache is enabled (CONFIG_4xx_DCACHE defined). The cache
won't be disabled by change_tlb before CPU POST because
there is an insufficient adress range check since
CFG_MEM_TOP_HIDE was introduced. This patch tries to fix
this problem.

Signed-off-by: Anatolij Gustschin <agust at denx.de>
---
 cpu/ppc4xx/tlb.c |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/cpu/ppc4xx/tlb.c b/cpu/ppc4xx/tlb.c
index 2bfcba1..f44822d 100644
--- a/cpu/ppc4xx/tlb.c
+++ b/cpu/ppc4xx/tlb.c
@@ -149,7 +149,9 @@ void change_tlb(u32 vaddr, u32 size, u32 tlb_word2_i_value)
 			/*
 			 * Now check the end-address if it's in the range
 			 */
-			if ((tlb_vaddr + tlb_size - 1) <= (vaddr + size - 1)) {
+			if (((tlb_vaddr + tlb_size - 1) <= (vaddr + size - 1)) ||
+			    ((tlb_vaddr < (vaddr + size - 1)) &&
+			     ((tlb_vaddr + tlb_size - 1) > (vaddr + size - 1)))) {
 				/*
 				 * Found a TLB in the range.
 				 * Change cache attribute in tlb2 word.
-- 
1.5.3.3