[U-Boot-Users] ppc4xx: gpio setup broken for ppc405ep

[Markus Brunner]

After some emails with John from AMCC here are the Results:

About the "random" tri-state select settings in the tables for alternate 
function for 440EP

> The values in the PPC440EP User's Manual (Revision 1.26 - March 20, 
> 2008) that's on the web look correct to me.
> Tables 29-6, 29-7 29-8 are 29-9 are all for alternate 1 signals. The
> GPIOn_TSRL/H can either be 0b00 or 0b01. This is what is in the manual.
> Tables 29-10, 29-11, 29-12 and 29-13 are all alternate 2 signals. 
> The GPIOn_TSRL/H can either be 0b00 or 0b10. This is what is in the 
> manual.
> Tables 29-14 is only contains alternate 3 signals.  The GPIOn_TSRL/H
> can either be 0b00 or 0b11. This is what is in the manual.
> 
> A setting of 0b00 means the settings in GPIOn_TCR control determine 
> whether a GPIO pin is tri-stated.
> A setting of 0b01 means the alternate 1 device attached internally 
> to the GPIO controller determine whether a GPIO pin is tri-stated.
> A setting of 0b10 means the alternate 2 device attached internally 
> to the GPIO controller determine whether a GPIO pin is tri-stated.
> A setting of 0b11 means the alternate 3 device attached internally 
> to the GPIO controller determine whether a GPIO pin is tri-stated.

I didn't get it at first, so in other words ...

> When the tri-state select bit field is set to 00 for a particular 
> GPIO signal, this just means the tri-state control for this signal 
> is controlled by the tri-state control register. If set to 01, 10 or
> 11, the alternate source for the signal is controlled by the 
> internal controller such as the UART or EBC.

The select registers just select the tri-state source. This can be consistent 
as for 405EX, but it can be random like for 440EP

And it can also be 00 all the time, like for 405EP

> The settings for GPIO0_TSRL in table 23-7 is correct. All the 
> GPIO0_TSRL bit fields are set to 0.

However my 405EP was working pretty well if I set the bitfields to 01 for alt 
function1.

The high/low addresses of the select registers of 405EP and the way they are 
assigned to the pins are like any other amcc processor. This means the 
current Users manual is wrong and will be updated.

> The original IBM 405EP manual made two errors. These two errors were
> self healing and have caused a confusing mess.
> 1. Table 23-1 assigned the high registers to low register addresses 
> and assigned the low registers to the high register addresses. The 
> lows and highs were exchanged.
> 2. Table 23-7 showed the high registers being configured when it 
> technically should have been the low registers.
> 
> Apparently a customer complained about the above two problems as it 
> confused them when using other PPC4XX parts. We fixed table 23-1 but
> we did not fix 23-7. Table 23-7 should use GPIO0_OSRL, GPIO0_TSRL, 
> and GPIO0_ISRL not GPIO0_OSRH, GPIO0_TSRH, and GPIO0_ISRH
> 
> I'll fix table 23-7 so that it uses GPIO0_OSRL, GPIO0_TSRL, and 
> GPIO0_ISRL. With this change the following register assignment makes
> sense and matches what is done on the 440EP/GR, 440EPx/GRx, 
> 405EX/EXr and 460EX/GT parts.
> 
> #define GPIO0_OR               (GPIO_BASE+0x0)
> #define GPIO0_TCR              (GPIO_BASE+0x4)
> #define GPIO0_OSRL             (GPIO_BASE+0x8)
> #define GPIO0_OSRH             (GPIO_BASE+0xC)
> #define GPIO0_TSRL            (GPIO_BASE+0x10)
> #define GPIO0_TSRH             (GPIO_BASE+0x14)
> #define GPIO0_ODR              (GPIO_BASE+0x18)
> #define GPIO0_IR               (GPIO_BASE+0x1C)
> #define GPIO0_RR1              (GPIO_BASE+0x20)
> #define GPIO0_RR2              (GPIO_BASE+0x24)
> #define GPIO0_ISR1L            (GPIO_BASE+0x30)
> #define GPIO0_ISR1H            (GPIO_BASE+0x34)
> #define GPIO0_ISR2L            (GPIO_BASE+0x38)
> #define GPIO0_ISR2H            (GPIO_BASE+0x3C)

So we've got to change something with the gpio setup.

Regards

Markus