[U-Boot-Users] PPC440EPx/sequoia TLB question...

[Josh Boyer]

On Thu, 2008-04-24 at 07:28 +0200, Stefan Roese wrote:
> On Thursday 24 April 2008, Dave Littell wrote:
> > >> Also the TLB entry for SDRAM marks it Guarded, but that’s one area I
> > >> would think wouldn't need to be Guarded.
> > >
> > > This could be a mistake. Should work without G bis set too. Please give
> > > it a try and send a patch to fix it, if it works fine.
> >
> > Hard to define "works fine" - this is the same 440EPx platform I'm
> > asking about over in the embedded Linux mailing list.  I'm pretty sure
> > the kernel doesn't flag SDRAM as Guarded,
> 
> Yes, and the 4xx code to dynamically set the SDRAM TLB's in the SPD code 
> doesn't set it either. So it really isn't needed.

Actually, that's not true for kernel memory.  We pin 256MiB TLBs to
cover lowmem in AS0, and the Guarded bit is set.  We set it to prevent
speculative access to memory holes where the 256MiB TLB covers more
address space than there is physical DRAM.

josh