[U-Boot-Users] pci memory booting on ppc460

[Stefan Roese]

On Thursday 24 April 2008, Ayman M. El-Khashab wrote:
> So maybe I need to clarify some more.  The PPC460 data sheet
> is not too clear on this yet.  However, here are my thoughts
> on this.  Lets just take the simple case as an example.  We
> have a plurality of 460s where a single one is the master.
> Between the master and all the slaves is a PCI bridge.  The
> slaves are hardwired to boot from pci bus memory -- according
> to the datasheet that is at a fixed address.  So there does
> not appear to be any need to do anything to the slave upon
> power up.  Now the master boots and then allocates a chunk
> of contiguous memory using a kernel driver or whatever is
> needed.  The image is just whatever the flash image would
> normally contain (uboot + kernel + rootfs).  The address of
> that chunk is then given to the pci bridge so that it can
> perform inbound translation from the address that the PPC
> slaves will use to the address where the image is physically
> located.  Then the slaves are taken out of reset and begin
> reading "flash" across the pci bus which really goes through
> the bridge and is mapped to the DRAM on the master (or I
> guess it could be the flash on the master, but DRAM seemed
> easier since it is already running).
>
> Ok, so how many holes does this approach have?

Sounds quite reasonable. The only thing I'm unsure here is the size of the PCI 
windows that is mapped upon PCI booting. The 460EX users manual doesn't 
mention anything about this, but from the 440EPx users manual this windows 
has the following size:

0xfffe.0000 - 0xffff.ffff -> 128kB

Not sure if this is the same on 460EX/GT. You should probably contact AMCC and 
ask about this.

If 128kB is correct, then this is a little short for a full-blown U-Boot 
image.

Best regards,
Stefan

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