[U-Boot] [PATCH] ppc4xx: Read pipeline depth set to 4 for PPC440SP/SPE, PPC405EX, PPC460EX/GT/SX processors

[Stefan Roese]

On Wednesday 13 August 2008, Wolfgang Denk wrote:
> > From: Prodyut Hazarika <phazarika at amcc.com>
> >
> > Signed-off-by: Prodyut Hazarika <phazarika at amcc.com>
> > Acked-by: Feng Kan <fkan at amcc.com>
> > ---
>
> It would be nice if the commit messages contained at least a minimal
> explanation of the reasons for the changes.

Yes, the original comment from Prodyut is gone. Please add it again.

<snip>

> > */ diff --git a/include/ppc4xx.h b/include/ppc4xx.h
> > index c71da60..154956e 100644
> > --- a/include/ppc4xx.h
> > +++ b/include/ppc4xx.h
> > @@ -46,6 +46,61 @@
> >  #define CONFIG_SDRAM_PPC4xx_IBM_DDR2	/* IBM DDR(2) controller */
> >  #endif
> >
> > +/* PLB4 CrossBar Arbiter Core supported across PPC4xx families */
> > +#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
> > +    defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
> > +    defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
> > +    defined(CONFIG_460EX) || defined(CONFIG_460GT)  || \
> > +    defined(CONFIG_460SX) || defined(CONFIG_405EX)
> > +
> > +#define PLB_ARBITER_BASE   0x80
> > +
> > +#define plb0_revid                (PLB_ARBITER_BASE+ 0x00)
> > +#define plb0_acr                  (PLB_ARBITER_BASE+ 0x01)
> > +#define   plb0_acr_ppm_mask             0xF0000000
> > +#define   plb0_acr_ppm_fixed            0x00000000
> > +#define   plb0_acr_ppm_fair             0xD0000000
> > +#define   plb0_acr_hbu_mask             0x08000000
> > +#define   plb0_acr_hbu_disabled         0x00000000
> > +#define   plb0_acr_hbu_enabled          0x08000000
> > +#define   plb0_acr_rdp_mask             0x06000000
> > +#define   plb0_acr_rdp_disabled         0x00000000
> > +#define   plb0_acr_rdp_2deep            0x02000000
> > +#define   plb0_acr_rdp_3deep            0x04000000
> > +#define   plb0_acr_rdp_4deep            0x06000000
> > +#define   plb0_acr_wrp_mask             0x01000000
> > +#define   plb0_acr_wrp_disabled         0x00000000
> > +#define   plb0_acr_wrp_2deep            0x01000000
> > +
> > +#define plb0_besrl                (PLB_ARBITER_BASE+ 0x02)
> > +#define plb0_besrh                (PLB_ARBITER_BASE+ 0x03)
> > +#define plb0_bearl                (PLB_ARBITER_BASE+ 0x04)
> > +#define plb0_bearh                (PLB_ARBITER_BASE+ 0x05)
> > +#define plb0_ccr                  (PLB_ARBITER_BASE+ 0x08)
> > +
> > +#define plb1_acr                  (PLB_ARBITER_BASE+ 0x09)
> > +#define   plb1_acr_ppm_mask             0xF0000000
> > +#define   plb1_acr_ppm_fixed            0x00000000
> > +#define   plb1_acr_ppm_fair             0xD0000000
> > +#define   plb1_acr_hbu_mask             0x08000000
> > +#define   plb1_acr_hbu_disabled         0x00000000
> > +#define   plb1_acr_hbu_enabled          0x08000000
> > +#define   plb1_acr_rdp_mask             0x06000000
> > +#define   plb1_acr_rdp_disabled         0x00000000
> > +#define   plb1_acr_rdp_2deep            0x02000000
> > +#define   plb1_acr_rdp_3deep            0x04000000
> > +#define   plb1_acr_rdp_4deep            0x06000000
> > +#define   plb1_acr_wrp_mask             0x01000000
> > +#define   plb1_acr_wrp_disabled         0x00000000
> > +#define   plb1_acr_wrp_2deep            0x01000000
> > +
> > +#define plb1_besrl                (PLB_ARBITER_BASE+ 0x0A)
> > +#define plb1_besrh                (PLB_ARBITER_BASE+ 0x0B)
> > +#define plb1_bearl                (PLB_ARBITER_BASE+ 0x0C)
> > +#define plb1_bearh                (PLB_ARBITER_BASE+ 0x0D)
> > +
> > +#endif /* 440EP/EPX 440GR/GRX 440SP/SPE 460EX/GT/SX 405EX*/
> > +
>
> Here you move 44x specific code from a 44x specific header file into a
> 4xx generic header file which requires you to add a 44x specific
> #ifdef's.

These defines are also used on the 405EX (and possibly future 405 variants as 
well). It makes sense to move them to ppc4xx.h so we don't have to duplicate 
those defines in 2 headers. This has been a big problem in the past with the 
ppc405.h and ppc440.h headers.

Best regards,
Stefan

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