[U-Boot] MPC83xx DDR Controller setup

[Kim Phillips]

On Tue, 26 Aug 2008 15:26:16 +0200
Andre Schwarz <andre.schwarz at matrix-vision.de> wrote:

> Kim,
> 
> can you (or anybody else) tell me what the following bit means on MPC834x ?
> Actually it's set inside the CLK_CNTL register of the DDR controller.
> It's completely missing in my (latest) datasheet's register definition ...
> 
> include/mpc83xx.h:#define DDR_SDRAM_CLK_CNTL_SS_EN              0x80000000

Hi Andre,

The mpc8349erm rev. 1 has it:

SS_EN Source synchronous enable
      0 Source synchronous is disabled.
      1 The address and command is sent to the DDR SDRAMs source synchronously. This bit must
        be set before enabling the DDR controller.

But in rev.3 of the chip (mpc8349EA rm rev. 1), the bit is obsoleted:

DDR_SDRAM_CLK_CNTL[SS_EN] has been removed from the MPC8349EA
and thus there is no effect of setting or clearing this bit. The device will work in
source sync mode by default.

Kim