[U-Boot-Users] Intel KIXRP435 platform
Antonello Lombardinilo
antonello at kasko.it
Fri Feb 8 20:37:44 CET 2008
Hi all,
I'am playing to porting u-boot to Intel KIXRP435 board
and starting from u-boot-ixp-HEAD from git.
I added kixrp435 platform cloning ixdp425 platform.
I modified a include/asm-arm/arch-ixp/ixp425.h and
cpu/ixp/start.S to initialize a DDR memory.
The compilation fail with following error:
make[1]: Entering directory
`/home/antonello/projects/u-boot/u-boot-ixp-new/cpu/ixp'
xscale_be-gcc -D__ASSEMBLY__ -g -Os -fno-strict-aliasing -fno-common
-ffixed-r8 -msoft-float -mbig-endian -D__KERNEL__ -DTEXT_BASE=0x00f80000
-I/home/antonello/projects/u-boot/u-boot-ixp-new/include -fno-builtin
-ffreestanding -nostdinc -isystem
/opt/mv5.0/montavista/pro/devkit/arm/xscale_be/bin/../lib/gcc/armv5teb-monta
vista-linux-gnueabi/4.2.0/include -pipe -DCONFIG_ARM -D__ARM__ -mbig-endian
-march=armv5te -mtune=strongarm1100 -mabi=apcs-gnu -c -o start.o start.S
start.S: Assembler messages:
start.S:527: Error: invalid constant (fffffbf4) after fixup
make[1]: *** [start.o] Error 1
make[1]: Leaving directory
`/home/antonello/projects/u-boot/u-boot-ixp-new/cpu/ixp'
make: *** [cpu/ixp/libixp.a] Error 2
[root at dhcppc0 u-boot-ixp-new]#
The problem seems due to the numbers of instruction in start.S file.
If I remove some instructions the compilation work fine.
I have attached a patch file. You can reproduce the problem removing
#define ERROR_AFTER_FIXUP statement in cpu/ixp/start.S file.
Any suggestions ?
Antonello
-------------- next part --------------
--- u-boot-ixp/cpu/ixp/start.S 2008-01-18 01:05:22.000000000 +0100
+++ u-boot-ixp-new/cpu/ixp/start.S 2008-02-08 20:15:37.000000000 +0100
@@ -165,48 +165,309 @@
orr r1, r1, #0x80000000
str r1, [r2]
#endif
- mov r1, #CFG_SDR_CONFIG
- ldr r2, =IXP425_SDR_CONFIG
- str r1, [r2]
+ /* Setup DDR controller */
+ ldr r0, =IXP_DDR_CFG_BASE1
+
+ ldr r1, =KIXRP435_SDCR0_INIT
+ str r1, [r0, #IXP_DDR_SDCR0]
- /* disable refresh cycles */
- mov r1, #0
- ldr r3, =IXP425_SDR_REFRESH
- str r1, [r3]
-
- /* send nop command */
- mov r1, #3
- ldr r4, =IXP425_SDR_IR
- str r1, [r4]
- DELAY_FOR 0x4000, r0
-
- /* set SDRAM internal refresh val */
- ldr r1, =CFG_SDRAM_REFRESH_CNT
- str r1, [r3]
- DELAY_FOR 0x4000, r0
-
- /* send precharge-all command to close all open banks */
- mov r1, #2
- str r1, [r4]
- DELAY_FOR 0x4000, r0
-
- /* provide 8 auto-refresh cycles */
- mov r1, #4
- mov r5, #8
-111: str r1, [r4]
- DELAY_FOR 0x100, r0
- subs r5, r5, #1
- bne 111b
-
- /* set mode register in sdram */
- mov r1, #CFG_SDR_MODE_CONFIG
- str r1, [r4]
- DELAY_FOR 0x4000, r0
-
- /* send normal operation command */
- mov r1, #6
- str r1, [r4]
- DELAY_FOR 0x4000, r0
+ ldr r1, =KIXRP435_SDCR1_INIT
+ str r1, [r0, #IXP_DDR_SDCR1]
+
+ mov r1, #CFG_DRAM_BASE
+ str r1, [r0, #IXP_DDR_SDBR]
+ ldr r1, [r0, #IXP_DDR_SDBR] /* readback */
+
+ ldr r1, =KIXRP435_SBR0_INIT
+ str r1, [r0, #IXP_DDR_SBR0]
+ ldr r1, [r0, #IXP_DDR_SBR0]
+
+ ldr r1, =KIXRP435_SBR1_INIT
+ str r1, [r0, #IXP_DDR_SBR1]
+ ldr r1, [r0, #IXP_DDR_SBR1]
+
+ /* Step 4. Disable refresh cycles */
+ mov r1, #0
+ str r1, [r0, #IXP_DDR_RFR]
+
+ /* Step 5. Send NOP command */
+ mov r1, #DDR_SDIR_NOP
+ str r1, [r0, #IXP_DDR_SDIR]
+
+ /* Step 6 */
+ DELAY_FOR 0x100000, r1
+
+ /* Step 7. Issue precharge-all command to close all open banks */
+ mov r1, #DDR_SDIR_PRECHARGE_ALL
+ str r1, [r0, #IXP_DDR_SDIR]
+ DELAY_FOR 0x100000, r1
+
+ /* Step 8. Issue an extended-mode-register2-set command */
+ mov r1, #DDR_SDIR_EMRS_2_SET_CMD
+ str r1, [r0, #IXP_DDR_SDIR]
+ DELAY_FOR 0x100000, r1
+
+ /* Step 9. Issue an extended-mode-register3-set command */
+ mov r1, #DDR_SDIR_EMRS_3_SET_CMD
+ str r1, [r0, #IXP_DDR_SDIR]
+ DELAY_FOR 0x100000, r1
+
+ /* Step 10. Issue extended mode register set to enable dll */
+ mov r1, #DDR_SDIR_EMRS_DLL_ENABLE
+ str r1, [r0, #IXP_DDR_SDIR]
+ DELAY_FOR 0x100000, r1
+
+ /* Step 11. Issue mode register set w/ DLL reset */
+ mov r1, #DDR_SDIR_MODE_SET_RESET
+ str r1, [r0, #IXP_DDR_SDIR]
+ DELAY_FOR 0x100000, r1
+
+ /* Step 12. Issue precharge-all command */
+ mov r1, #DDR_SDIR_PRECHARGE_ALL
+ str r1, [r0, #IXP_DDR_SDIR]
+ DELAY_FOR 0x100000, r1
+
+ /* Step 13. provide 2 auto-refresh cycles */
+ mov r1, #DDR_SDIR_AUTO_REFRESH
+ mov r2, #2
+ 1:
+ str r1, [r0, #IXP_DDR_SDIR]
+ ldr r3, [r0, #IXP_DDR_SDIR]
+ DELAY_FOR 0x800, r3
+ subs r2, r2, #1
+ bne 1b
+
+ /* Step 14. Issue mode register set w/o DLL reset */
+ mov r1, #DDR_SDIR_MODE_SET_NO_RESET
+ str r1, [r0, #IXP_DDR_SDIR]
+ DELAY_FOR 0x100000, r1
+
+ /* Step 15. Start normal operation */
+ mov r1, #0xf
+ str r1, [r0, #IXP_DDR_SDIR]
+ DELAY_FOR 0x10000, r1
+
+ /* Step 16. Set refresh val */
+ ldr r1, =KIXRP435_SDRAM_REFRESH_CNT
+ str r1, [r0, #IXP_DDR_RFR]
+ DELAY_FOR 0x100000, r1
+
+ /* Additional setup for SDRAM controller */
+ ldr r0, =IXP_DDR_CFG_BASE2
+
+ ldr r1, = 0x00000004
+ str r1, [r0, #IXP_DDR_RCVDLY]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x00000000
+ str r1, [r0, #IXP_DDR_SLVLMIX0]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x00000000
+ str r1, [r0, #IXP_DDR_SLVLMIX1]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x00000000
+ str r1, [r0, #IXP_DDR_SLVHMIX0]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x00000000
+ str r1, [r0, #IXP_DDR_SLVHMIX1]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x00000004
+ str r1, [r0, #IXP_DDR_SLVLEN]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x00000000
+ str r1, [r0, #IXP_DDR_MASTMIX]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x0000000a
+ str r1, [r0, #IXP_DDR_LEGOVERIDE]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x0002D400
+ str r1, [r0, #IXP_DDR_DDRMISCTL]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x0002D400
+ str r1, [r0, #IXP_DDR_DDRMISCTL]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x0002D400
+ str r1, [r0, #IXP_DDR_DDRMISCTL]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x0002D400
+ str r1, [r0, #IXP_DDR_DDRMISCTL]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x0002D400
+ str r1, [r0, #IXP_DDR_DDRMISCTL]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x0002D400
+ str r1, [r0, #IXP_DDR_DDRMISCTL]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x0002D400
+ str r1, [r0, #IXP_DDR_DDRMISCTL]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x0000889C
+ str r1, [r0, #IXP_DDR_HM_WRCAL]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x0000889C
+ str r1, [r0, #IXP_DDR_HM_WRCAL]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x0000889C
+ str r1, [r0, #IXP_DDR_HM_WRCAL]
+ DELAY_FOR 0x100000, r1
+
+#if ERROR_AFTER_FIXUP
+ ldr r1, = 0x0000889C
+ str r1, [r0, #IXP_DDR_HM_WRCAL]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x0000889C
+ str r1, [r0, #IXP_DDR_HM_WRCAL]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x0000809C
+ str r1, [r0, #IXP_DDR_HM_WRCAL]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x81000006
+ str r1, [r0, #IXP_DDR_DCALCSR]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x81000106
+ str r1, [r0, #IXP_DDR_DCALCSR]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x81000206
+ str r1, [r0, #IXP_DDR_DCALCSR]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x81000306
+ str r1, [r0, #IXP_DDR_DCALCSR]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x81000406
+ str r1, [r0, #IXP_DDR_DCALCSR]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x81000506
+ str r1, [r0, #IXP_DDR_DCALCSR]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x81000606
+ str r1, [r0, #IXP_DDR_DCALCSR]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x81000706
+ str r1, [r0, #IXP_DDR_DCALCSR]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x81002006
+ str r1, [r0, #IXP_DDR_DCALCSR]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x81002106
+ str r1, [r0, #IXP_DDR_DCALCSR]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x81002206
+ str r1, [r0, #IXP_DDR_DCALCSR]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x81002306
+ str r1, [r0, #IXP_DDR_DCALCSR]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x81002406
+ str r1, [r0, #IXP_DDR_DCALCSR]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x81002506
+ str r1, [r0, #IXP_DDR_DCALCSR]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x81002606
+ str r1, [r0, #IXP_DDR_DCALCSR]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x81002706
+ str r1, [r0, #IXP_DDR_DCALCSR]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x81004006
+ str r1, [r0, #IXP_DDR_DCALCSR]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x81004106
+ str r1, [r0, #IXP_DDR_DCALCSR]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x81004206
+ str r1, [r0, #IXP_DDR_DCALCSR]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x81004306
+ str r1, [r0, #IXP_DDR_DCALCSR]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x81004406
+ str r1, [r0, #IXP_DDR_DCALCSR]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x81004506
+ str r1, [r0, #IXP_DDR_DCALCSR]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x81004606
+ str r1, [r0, #IXP_DDR_DCALCSR]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x81004706
+ str r1, [r0, #IXP_DDR_DCALCSR]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x81006006
+ str r1, [r0, #IXP_DDR_DCALCSR]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x81006106
+ str r1, [r0, #IXP_DDR_DCALCSR]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x81006206
+ str r1, [r0, #IXP_DDR_DCALCSR]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x81006306
+ str r1, [r0, #IXP_DDR_DCALCSR]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x81006406
+ str r1, [r0, #IXP_DDR_DCALCSR]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x81006506
+ str r1, [r0, #IXP_DDR_DCALCSR]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x81006606
+ str r1, [r0, #IXP_DDR_DCALCSR]
+ DELAY_FOR 0x100000, r1
+
+ ldr r1, = 0x81006706
+ str r1, [r0, #IXP_DDR_DCALCSR]
+ DELAY_FOR 0x100000, r1
+#endif
/* copy */
mov r0, #0
-------------- next part --------------
--- u-boot-ixp/include/asm-arm/arch-ixp/ixp425.h 2008-01-18 01:05:22.000000000 +0100
+++ u-boot-ixp-new/include/asm-arm/arch-ixp/ixp425.h 2008-02-08 18:39:16.000000000 +0100
@@ -178,6 +178,101 @@
#define IXP425_SDR_IR IXP425_SDRAM_REG(IXP425_SDR_IR_OFFSET)
/*
+ * DDR register (IXP43X - IXP46X)
+ */
+#define IXP_DDR_CFG_BASE1 0xCC00E500
+#define IXP_DDR_CFG_BASE2 0xCC00F500
+
+#define IXP_DDR_SDIR 0x00
+#define IXP_DDR_SDCR0 0x04
+#define IXP_DDR_SDCR1 0x08
+#define IXP_DDR_SDBR 0x0C
+#define IXP_DDR_SBR0 0x10
+#define IXP_DDR_SBR1 0x14
+#define IXP_DDR_S32SR 0x18
+#define IXP_DDR_ECCR 0x1C
+#define IXP_DDR_ELOG0 0x20
+#define IXP_DDR_ELOG1 0x24
+#define IXP_DDR_ECAR0 0x28
+#define IXP_DDR_ECAR1 0x2C
+#define IXP_DDR_ECTST 0x30
+#define IXP_DDR_MCISR 0x34
+#define IXP_DDR_MACR 0x38
+#define IXP_DDR_MPTCR 0x3C
+#define IXP_DDR_MPCR 0x40
+#define IXP_DDR_RFR 0x48
+#define IXP_DDR_SDPR0 0x50
+#define IXP_DDR_SDPR1 0x54
+#define IXP_DDR_SDPR2 0x58
+#define IXP_DDR_SDPR3 0x5C
+#define IXP_DDR_SDPR4 0x60
+#define IXP_DDR_SDPR5 0x64
+#define IXP_DDR_SDPR6 0x68
+#define IXP_DDR_SDPR7 0x6C
+
+#define IXP_DDR_DCALCSR 0x00
+#define IXP_DDR_RCVDLY 0x50
+#define IXP_DDR_SLVLMIX0 0x54
+#define IXP_DDR_SLVLMIX1 0x58
+#define IXP_DDR_SLVHMIX0 0x5c
+#define IXP_DDR_SLVHMIX1 0x60
+#define IXP_DDR_SLVLEN 0x64
+#define IXP_DDR_MASTMIX 0x68
+#define IXP_DDR_LEGOVERIDE 0x74
+#define IXP_DDR_DDRMISCTL 0x78
+#define IXP_DDR_HM_WRCAL 0x7c
+
+/* SDIR command values */
+#define DDR_SDIR_MODE_SET_NO_RESET 0
+#define DDR_SDIR_MODE_SET_RESET 1
+#define DDR_SDIR_PRECHARGE_ALL 2
+#define DDR_SDIR_NOP 3
+#define DDR_SDIR_EMRS_DLL_ENABLE 4
+#define DDR_SDIR_EMRS_DLL_DISABLE 5
+#define DDR_SDIR_AUTO_REFRESH 6
+#define DDR_SDIR_EMRS_2_SET_CMD 7
+#define DDR_SDIR_EMRS_3_SET_CMD 8
+
+/* SDCR0 bits */
+#define DDR_SDCR0_TRAS(x) ((x)<<28)
+#define DDR_SDCR0_TRP(x) ((x)<<24)
+#define DDR_SDCR0_TRCD(x) ((x)<<20)
+#define DDR_SDCR0_TEDP(x) ((x)<<16)
+#define DDR_SDCR0_TWL(x) ((x)<<12)
+#define DDR_SDCR0_CAS_2 (0 << 8)
+#define DDR_SDCR0_CAS_2_5 (1 << 8)
+#define DDR_SDCR0_ODT_DISABLED (0 << 4)
+#define DDR_SDCR0_ODT_75 (1 << 4)
+#define DDR_SDCR0_ODT_150 (2 << 4)
+#define DDR_SDCR0_DDR_I (1 << 2)
+#define DDR_SDCR0_BUS32 (1 << 1)
+
+/* SDCR1 bits */
+#define DDR_SDCR1_TRTCMD(x) ((x)<<28)
+#define DDR_SDCR1_TWTCMD(x) ((x)<<24)
+#define DDR_SDCR1_TRTW(x) ((x)<<20)
+#define DDR_SDCR1_TRFC(x) ((x)<<12)
+#define DDR_SDCR1_TWR(x) ((x)<<9)
+#define DDR_SDCR1_TRC(x) ((x)<<4)
+#define DDR_SDCR1_TWTRD(x) ((x)<<0)
+
+/* SBR0/1 bits */
+#define DDR_SBR_128Mx8 (0<<30)
+#define DDR_SBR_128Mx16 (0<<30)
+#define DDR_SBR_256Mx8 (0<<30)
+#define DDR_SBR_512Mx8 (0<<30)
+#define DDR_SBR_512Mx16 (0<<30)
+#define DDR_SBR_1Gx8 (0<<30)
+#define DDR_SBR_256Mx16 (2<<30)
+#define DDR_SBR_1Gx16 (3<<30)
+
+/* ECCR bits */
+#define DDR_ECCR_ENABLE (1 << 3)
+#define DDR_ECCR_SBEC (1 << 2)
+#define DDR_ECCR_MBER (1 << 1)
+#define DDR_ECCR_SBER (1 << 0)
+
+/*
* UART registers
*/
#define IXP425_UART1 0
More information about the U-Boot
mailing list