[U-Boot-Users] Problems with new ethernet init on mpc8360

Joakim Tjernlund Joakim.Tjernlund at transmode.se
Tue Feb 26 20:55:42 CET 2008


> -----Original Message-----
> From: u-boot-users-bounces at lists.sourceforge.net [mailto:u-boot-users-bounces at lists.sourceforge.net]
> On Behalf Of Jerry Van Baren
> Sent: den 26 februari 2008 19:41
> To: Kim Phillips
> Cc: U-Boot Users
> Subject: Re: [U-Boot-Users] Problems with new ethernet init on mpc8360
> 
> Jerry Van Baren wrote:
> > Jerry Van Baren wrote:
> >> Kim Phillips wrote:
> >>> On Mon, 25 Feb 2008 22:55:37 -0500
> >>> Jerry Van Baren <gvb.uboot at gmail.com> wrote:
> >>>
> >>>> Hi Kim,
> >>>>
> >>>> I have a mpc8360emds eval board.  The ee62ed patch (below) speeds up the
> >>>> start up (good), but seems to cause the board to hang on the *second*
> >>>> ethernet operation.
> >>>>
> >>>> I can cause this by doing two pings in a row: the first ping initializes
> >>>> the network and completes successfully.  The second ping hangs the
> >>>> board: it never completes.  I cannot abort it with ^C.  The only way out
> >>>> is to reset the board.
> >>>>
> >>>> The same thing happens with two back-to-back tftp operations or a ping
> >>>> followed by a tftp operation.
> >>>>
> >>>> If I back out the ee62ed patch (below), it "fixes" the problem.
> >>>>
> >>>> I tried backing out some simple portions of the patch (added delays back
> >>>> in) with no success.  I've given up chasing this for tonight.  Any
> >>>> inspiration you can generate would be appreciated, I'll chase it some
> >>>> more tomorrow.
> >>> I verified rc2 on rev. 1.1 and 2.1 boards pings more than once.
> >>>
> >>> can you provide more details about which u-boot version, what board rev
> >>> you're on, what kind of connection you're using, speed, etc.?
> >>>
> >>> Kim
> >> OK, I confirmed it was operator error by doing a clean clone and rebuild
> >> of u-boot.
> >>
> >> Sorry for the noise,
> >> gvb
> >
> > My bad, the noise *wasn't* noise.  What worked for me was 1.3.1 (above
> > results), which initializes the ethernet on start up.  When I cloned the
> > u-boot repo (or u-boot-testing), the second ping hangs the board for me.
> >
> > Is the fact that I don't have a valid env a clue (I have never bothered
> > to save an env)?  Hmmmm, what env variables could be messing me up?  I
> > would suspect the ethernet rotation one.  I don't have the second
> > etherspiggot plugged in, but that should simply fail and rotate back to
> > the first etherspiggot (scratches head).
> >
> > Thanks,
> > gvb
> >
> >
> > U-Boot 1.3.2-rc2 (Feb 26 2008 - 13:21:20) MPC83XX
> >
> > Reset Status: Software Hard, External/Internal Soft, External/Internal Hard
> >
> > CPU:   e300c1, MPC8360E, Rev: 12 at 528 MHz, CSB:  264 MHz
> > Board: Freescale MPC8360EMDS
> > I2C:   ready
> > DRAM:  256 MB (DDR1, 64-bit, ECC off)
> > SDRAM: 64 MB (local bus)
> > PCI 32bit bus on PMC1 & PMC2 &PMC3
> > FLASH: 16 MB
> > *** Warning - bad CRC, using default environment
> >
> > PCI clock is 66MHz
> > In:    serial
> > Out:   serial
> > Err:   serial
> > Net:   FSL UEC0, FSL UEC1
> > Hit any key to stop autoboot:  0
> >
> > => set serverip 192.168.47.8 ; set ipaddr 192.168.47.214
> >
> > => ping 192.168.47.8
> > UEC: PHY is Marvell 88E11x1 (1410cc2)
> > FSL UEC0: Full Duplex
> > switching to rgmii 100
> > FSL UEC0: Speed 100BT
> > FSL UEC0: Link is up
> > Using FSL UEC0 device
> > host 192.168.47.8 is alive
> >
> > => ping 192.168.47.8
> 
> Sorry, I should have included the default environment contents for
> reference:
> 
> => printenv
> bootcmd=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath
> ip=$ipaddrr
> ramboot=setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate
> $othbootr
> nfsboot=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath
> ip=$ipaddrr
> bootdelay=6
> baudrate=115200
> loads_echo=1
> ethaddr=00:04:9f:ef:01:01
> eth1addr=00:04:9f:ef:01:02
> loadaddr=200000
> netdev=eth0
> consoledev=ttyS0
> ramdiskaddr=1000000
> ramdiskfile=ramfs.83xx
> fdtaddr=400000
> fdtfile=mpc8360emds.dtb
> stdin=serial
> stdout=serial
> stderr=serial
> ethact=FSL UEC0
> 
> Environment size: 979/8188 bytes

Maybe you suffer from something I noticed, sometimes the master for MDIO gets
out of sync. Try this patch and see if it helps, not sure if it still applies
but that should be easy to fix up.


>From 241d7e4f4fb26b2424311a6012c845bd97dfdafa Mon Sep 17 00:00:00 2001
From: Joakim Tjernlund <Joakim.Tjernlund at transmode.se>
Date: Tue, 18 Dec 2007 14:33:18 +0100
Subject: [PATCH] Move call to qe_set_mii_clk_src() into uec_read_phy_reg() and
 uec_write_phy_reg() to make sure MII master clock source is
 correct.

---
 drivers/qe/uec.c     |    5 -----
 drivers/qe/uec_phy.c |    6 ++++++
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index 01db88a..4908798 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -479,8 +479,6 @@ static int init_phy(struct eth_device *dev)
 
 	uec->mii_info = mii_info;
 
-	qe_set_mii_clk_src(uec->uec_info->uf_info.ucc_num);
-
 	if (init_mii_management_configuration(umii_regs)) {
 		printf("%s: The MII Bus is stuck!", dev->name);
 		err = -1;
@@ -1012,9 +1010,6 @@ static int uec_startup(uec_private_t *uec)
 	uec->uec_mii_regs = (uec_mii_t *) CONFIG_MIIM_ADDRESS;
 #endif
 
-	/* Setup MII master clock source */
-	qe_set_mii_clk_src(uec_info->uf_info.ucc_num);
-
 	/* Setup UTBIPAR */
 	utbipar = in_be32(&uec_regs->utbipar);
 	utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK;
diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c
index ecb6133..efb2574 100644
--- a/drivers/qe/uec_phy.c
+++ b/drivers/qe/uec_phy.c
@@ -66,6 +66,9 @@ void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int valu
 	enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
 	u32 tmp_reg;
 
+	/* Setup MII master clock source */
+	qe_set_mii_clk_src(ugeth->uec_info->uf_info.ucc_num);
+
 	ug_regs = ugeth->uec_mii_regs;
 
 	/* Stop the MII management read cycle */
@@ -94,6 +97,9 @@ int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum)
 	u32 tmp_reg;
 	u16 value;
 
+	/* Setup MII master clock source */
+	qe_set_mii_clk_src(ugeth->uec_info->uf_info.ucc_num);
+
 	ug_regs = ugeth->uec_mii_regs;
 
 	/* Setting up the MII Mangement Address Register */
-- 
1.5.3.7


 





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