[U-Boot-Users] Accessing IRAM & DRAM through different segments in MIPS

[Shinya Kuribayashi]

Viswanath Bandi wrote:
> I am trying to run U-boot on a MIPS 4KEc processor mapped onto FPGA. The 
> code is working fine when KSEG0 is configured as un-cached segment (K0 
> field in CP0 register 16 configured as 2). But when I make this as 
> cached segment, the code crashes and I see that the values on the stack 
> are not written correctly. Due to this the program causes some exception 
> or the other.

Ok.

> In order to isolate the problem between icache and dcache, I want to try 
> and access IRAM using KSEG1 addresses (0xA0000000 onwards) and DRAM 
> using KSEG0 addresses (0x80000000) or vice versa. Is the possible? Can 

IMHO it's possible but very hard to do, and

> it be done through some configuration changes or #defines? This way I 

we don't have such debugging alternatives, sorry.

> can find out whether instruction is the culprit for not writing the 
> value in memory or the data cache.

How do you configure 4KEc caches? I'm interested in 1) its size and 2)
the numbers of its ways. Hmm, some ideas come to mind. For the first
setp does attached patch work for you?

diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S
index 443240e..05735f4 100644
--- a/cpu/mips/cache.S
+++ b/cpu/mips/cache.S
@@ -29,10 +29,10 @@
 #include <asm/addrspace.h>
 #include <asm/cacheops.h>
 
-	/* 16KB is the maximum size of instruction and data caches on
-	 * MIPS 4K.
+	/* 64KB is the maximum size of instruction and data caches on
+	 * MIPS 4KE.
 	 */
-#define MIPS_MAX_CACHE_SIZE	0x4000
+#define MIPS_MAX_CACHE_SIZE	0x10000
 
 /*
  * cacheop macro to automate cache operations