[U-Boot-Users] Accessing IRAM & DRAM through different segments in MIPS

[Hoi-Ho Chan]

I had a similar problem with running U-boot on a 4KEc processor on
cached memory, u-boot got stuck after display the memory sizes. Then I
added a routine like this:

ulong start_addr = KSEG0;
ulong end_addr = start_addr + CFG_DCACHE_SIZE;

while (start_addr < end_addr) {
    __asm__ __voltaile__(".set noreorder; \
                                     .set mips3; \
                                     cache %1, (%0);
                                     .set mips0;
                                     .set reorder"::"r"(start_addr),
"i"(Index_Writeback_Inv_D));

    start_addr += CFG_CACHELINE_SIZE;
}

and then call it at lib_mips/board.c right before relocate_code(...)

seems to work for me.

Thanks
Donald

On Jan 5, 2008 4:55 AM, Viswanath Bandi <bandiv at txc.stpn.soft.net> wrote:
> Hi All,
>
> I am trying to run U-boot on a MIPS 4KEc processor mapped onto FPGA. The
> code is working fine when KSEG0 is configured as un-cached segment (K0
> field in CP0 register 16 configured as 2). But when I make this as
> cached segment, the code crashes and I see that the values on the stack
> are not written correctly. Due to this the program causes some exception
> or the other.
>
> In order to isolate the problem between icache and dcache, I want to try
> and access IRAM using KSEG1 addresses (0xA0000000 onwards) and DRAM
> using KSEG0 addresses (0x80000000) or vice versa. Is the possible? Can
> it be done through some configuration changes or #defines? This way I
> can find out whether instruction is the culprit for not writing the
> value in memory or the data cache.
>
> I would very much appreciate any information in this regard.
>
> Best Regards,
> Viswanath Bandi
>
>
>
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