[U-Boot-Users] [PATCH 1/2] mpc85xx: Add support for SBC8548 (updated)
Andy Fleming
afleming at gmail.com
Wed Jan 9 08:56:03 CET 2008
Applied both, thanks!
Just so you know, I modified init.S to conform to Kumar's TLB macro
changes. There shouldn't be any breakage, but take a look at the 85xx
repo to confirm.
On 12/13/07, Joe Hamman <joe.hamman at embeddedspecialties.com> wrote:
> Add support for Wind River's SBC8548 reference board.
>
> Signed-off by: Joe Hamman <joe.hamman at embeddedspecialties.com>
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index b8c1fdc..ac11985 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -190,6 +190,7 @@ Howard Gray <mvsensor at matrix-vision.de>
>
> Joe Hamman <joe.hamman at embeddedspecialties.com>
>
> + sbc8548 MPC8548
> sbc8641d MPC8641D
>
> Klaus Heydeck <heydeck at kieback-peter.de>
> diff --git a/MAKEALL b/MAKEALL
> index a02412b..bb97e2a 100755
> --- a/MAKEALL
> +++ b/MAKEALL
> @@ -328,6 +328,7 @@ LIST_85xx=" \
> PM854 \
> PM856 \
> sbc8540 \
> + sbc8548 \
> sbc8560 \
> stxgp3 \
> stxssa \
> diff --git a/Makefile b/Makefile
> index bde38ca..75841c0 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -1992,6 +1992,9 @@ sbc8540_66_config: unconfig
> fi
> @$(MKCONFIG) -a SBC8540 ppc mpc85xx sbc8560
>
> +sbc8548_config: unconfig
> + @$(MKCONFIG) $(@:_config=) ppc mpc85xx sbc8548
> +
> sbc8560_config \
> sbc8560_33_config \
> sbc8560_66_config: unconfig
> diff --git a/board/sbc8548/Makefile b/board/sbc8548/Makefile
> new file mode 100644
> index 0000000..1596525
> --- /dev/null
> +++ b/board/sbc8548/Makefile
> @@ -0,0 +1,55 @@
> +#
> +# (C) Copyright 2004-2006
> +# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> +#
> +# (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
> +# Added support for Wind River SBC8560 board
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +
> +include $(TOPDIR)/config.mk
> +
> +LIB = $(obj)lib$(BOARD).a
> +
> +COBJS := $(BOARD).o
> +SOBJS := init.o
> +#SOBJS :=
> +
> +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
> +OBJS := $(addprefix $(obj),$(COBJS))
> +SOBJS := $(addprefix $(obj),$(SOBJS))
> +
> +$(LIB): $(obj).depend $(OBJS) $(SOBJS)
> + $(AR) $(ARFLAGS) $@ $(OBJS)
> +
> +clean:
> + rm -f $(OBJS) $(SOBJS)
> +
> +distclean: clean
> + rm -f $(LIB) core *.bak .depend
> +
> +#########################################################################
> +
> +# defines $(obj).depend target
> +include $(SRCTREE)/rules.mk
> +
> +sinclude $(obj).depend
> +
> +#########################################################################
> diff --git a/board/sbc8548/config.mk b/board/sbc8548/config.mk
> new file mode 100644
> index 0000000..c9fa3ad
> --- /dev/null
> +++ b/board/sbc8548/config.mk
> @@ -0,0 +1,32 @@
> +#
> +# Copyright 2004, 2007 Freescale Semiconductor.
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +
> +#
> +# sbc8548 board
> +#
> +ifndef TEXT_BASE
> +TEXT_BASE = 0xfff80000
> +endif
> +
> +PLATFORM_CPPFLAGS += -DCONFIG_E500=1
> +PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
> +PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1
> diff --git a/board/sbc8548/init.S b/board/sbc8548/init.S
> new file mode 100644
> index 0000000..716057e
> --- /dev/null
> +++ b/board/sbc8548/init.S
> @@ -0,0 +1,247 @@
> +/*
> + * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
> + * Copyright 2007 Embedded Specialties, Inc.
> + *
> + * Copyright 2004 Freescale Semiconductor.
> + * Copyright 2002,2003, Motorola Inc.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <ppc_asm.tmpl>
> +#include <ppc_defs.h>
> +#include <asm/cache.h>
> +#include <asm/mmu.h>
> +#include <config.h>
> +#include <mpc85xx.h>
> +
> +
> +/*
> + * TLB0 and TLB1 Entries
> + *
> + * Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
> + * However, CCSRBAR is then relocated to CFG_CCSRBAR right after
> + * these TLB entries are established.
> + *
> + * The TLB entries for DDR are dynamically setup in spd_sdram()
> + * and use TLB1 Entries 8 through 15 as needed according to the
> + * size of DDR memory.
> + *
> + * MAS0: tlbsel, esel, nv
> + * MAS1: valid, iprot, tid, ts, tsize
> + * MAS2: epn, sharen, x0, x1, w, i, m, g, e
> + * MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
> + */
> +
> +#define entry_start \
> + mflr r1 ; \
> + bl 0f ;
> +
> +#define entry_end \
> +0: mflr r0 ; \
> + mtlr r1 ; \
> + blr ;
> +
> + .section .bootpg, "ax"
> + .globl tlb1_entry
> +
> +tlb1_entry:
> + entry_start
> +
> + /*
> + * Number of TLB0 and TLB1 entries in the following table
> + */
> + .long 13
> +
> +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
> + /*
> + * TLB0 4K Non-cacheable, guarded
> + * 0xff700000 4K Initial CCSRBAR mapping
> + *
> + * This ends up at a TLB0 Index==0 entry, and must not collide
> + * with other TLB0 Entries.
> + */
> + .long TLB1_MAS0(0, 0, 0)
> + .long TLB1_MAS1(1, 0, 0, 0, 0)
> + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0)
> + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1)
> +#else
> +#error("Update the number of table entries in tlb1_entry")
> +#endif
> +
> + /*
> + * TLB0 16K Cacheable, non-guarded
> + * 0xe4010000 16K Temporary Global data for initialization
> + *
> + * Use four 4K TLB0 entries. These entries must be cacheable
> + * as they provide the bootstrap memory before the memory
> + * controler and real memory have been configured.
> + *
> + * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
> + * and must not collide with other TLB0 entries.
> + */
> + .long TLB1_MAS0(0, 0, 0)
> + .long TLB1_MAS1(1, 0, 0, 0, 0)
> + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
> + 0,0,0,0,0,0,0,0)
> + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
> + 0,0,0,0,0,1,0,1,0,1)
> +
> + .long TLB1_MAS0(0, 0, 0)
> + .long TLB1_MAS1(1, 0, 0, 0, 0)
> + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
> + 0,0,0,0,0,0,0,0)
> + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
> + 0,0,0,0,0,1,0,1,0,1)
> +
> + .long TLB1_MAS0(0, 0, 0)
> + .long TLB1_MAS1(1, 0, 0, 0, 0)
> + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
> + 0,0,0,0,0,0,0,0)
> + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
> + 0,0,0,0,0,1,0,1,0,1)
> +
> + .long TLB1_MAS0(0, 0, 0)
> + .long TLB1_MAS1(1, 0, 0, 0, 0)
> + .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
> + 0,0,0,0,0,0,0,0)
> + .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
> + 0,0,0,0,0,1,0,1,0,1)
> +
> + /*
> + * TLB 0: 16M Non-cacheable, guarded
> + * 0xff800000 16M TLB for 8MB FLASH
> + * Out of reset this entry is only 4K.
> + */
> + .long TLB1_MAS0(1, 0, 0)
> + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
> + .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
> + .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
> +
> + /*
> + * TLB 1: 256M Non-cacheable, guarded
> + * 0x80000000 256M PCI1 MEM First half
> + */
> + .long TLB1_MAS0(1, 1, 0)
> + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
> + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
> + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
> +
> + /*
> + * TLB 2: 256M Non-cacheable, guarded
> + * 0x90000000 256M PCI1 MEM Second half
> + */
> + .long TLB1_MAS0(1, 2, 0)
> + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
> + .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
> + 0,0,0,0,1,0,1,0)
> + .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
> + 0,0,0,0,0,1,0,1,0,1)
> +
> + /*
> + * TLB 3: 256M Cacheable, non-guarded
> + * 0x0 256M DDR SDRAM
> + */
> + #if !defined(CONFIG_SPD_EEPROM)
> + .long TLB1_MAS0(1, 3, 0)
> + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
> + .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
> + .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
> + #endif
> +
> + /*
> + * TLB 4: 64M Non-cacheable, guarded
> + * 0xe0000000 1M CCSRBAR
> + * 0xe2000000 16M PCI1 IO
> + */
> + .long TLB1_MAS0(1, 4, 0)
> + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
> + .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
> + .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
> +
> + /*
> + * TLB 5: 64M Cacheable, non-guarded
> + * 0xf0000000 64M LBC SDRAM
> + */
> + .long TLB1_MAS0(1, 5, 0)
> + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
> + .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
> + .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
> +
> + /*
> + * TLB 6: 16M Cacheable, non-guarded
> + * 0xf8000000 1M 7-segment LED display
> + * 0xf8100000 1M User switches
> + * 0xf8300000 1M Board revision
> + * 0xf8b00000 1M EEPROM
> + */
> + .long TLB1_MAS0(1, 6, 0)
> + .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
> + .long TLB1_MAS2(E500_TLB_EPN(CFG_EPLD_BASE), 0,0,0,0,0,0,0,0)
> + .long TLB1_MAS3(E500_TLB_RPN(CFG_EPLD_BASE), 0,0,0,0,0,1,0,1,0,1)
> +
> + entry_end
> +
> +/*
> + * LAW(Local Access Window) configuration:
> + *
> + * 0x0000_0000 0x0fff_ffff DDR 256M
> + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
> + * 0xe000_0000 0xe000_ffff CCSR 1M
> + * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
> + * 0xf000_0000 0xf7ff_ffff SDRAM 128M
> + * 0xf8b0_0000 0xf80f_ffff EEPROM 1M
> + * 0xfb80_0000 0xff7f_ffff FLASH (2nd bank) 64M
> + * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
> + *
> + * Notes:
> + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
> + * If flash is 8M at default position (last 8M), no LAW needed.
> + *
> + * The defines below are 1-off of the actual LAWAR0 usage.
> + * So LAWAR3 define uses the LAWAR4 register in the ECM.
> + */
> +
> +
> +#if !defined(CONFIG_SPD_EEPROM)
> + #define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
> + #define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M))
> +#else
> + #define LAWBAR0 0
> + #define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M)) & ~LAWAR_EN)
> +#endif
> +
> +#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
> +#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
> +
> +#define LAWBAR2 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
> +#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
> +
> +/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
> +#define LAWBAR3 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
> +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
> +
> + .section .bootpg, "ax"
> + .globl law_entry
> +
> +law_entry:
> + entry_start
> + .long 4
> + .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
> + entry_end
> diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
> new file mode 100644
> index 0000000..7b44152
> --- /dev/null
> +++ b/board/sbc8548/sbc8548.c
> @@ -0,0 +1,569 @@
> +/*
> + * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
> + * Copyright 2007 Embedded Specialties, Inc.
> + *
> + * Copyright 2004, 2007 Freescale Semiconductor.
> + *
> + * (C) Copyright 2002 Scott McNutt <smcnutt at artesyncp.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <pci.h>
> +#include <asm/processor.h>
> +#include <asm/immap_85xx.h>
> +#include <asm/immap_fsl_pci.h>
> +#include <spd.h>
> +#include <miiphy.h>
> +#include <libfdt.h>
> +#include <fdt_support.h>
> +
> +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
> +extern void ddr_enable_ecc(unsigned int dram_size);
> +#endif
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +extern long int spd_sdram(void);
> +
> +void local_bus_init(void);
> +void sdram_init(void);
> +long int fixed_sdram (void);
> +
> +int board_early_init_f (void)
> +{
> + return 0;
> +}
> +
> +int checkboard (void)
> +{
> + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
> + volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
> +
> + printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
> + (volatile)(*(u_char *)CFG_BD_REV) >> 4);
> +
> + /*
> + * Initialize local bus.
> + */
> + local_bus_init ();
> +
> + /*
> + * Fix CPU2 errata: A core hang possible while executing a
> + * msync instruction and a snoopable transaction from an I/O
> + * master tagged to make quick forward progress is present.
> + */
> + ecm->eebpcr |= (1 << 16);
> +
> + /*
> + * Hack TSEC 3 and 4 IO voltages.
> + */
> + gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
> +
> + ecm->eedr = 0xffffffff; /* clear ecm errors */
> + ecm->eeer = 0xffffffff; /* enable ecm errors */
> + return 0;
> +}
> +
> +long int
> +initdram(int board_type)
> +{
> + long dram_size = 0;
> +
> + puts("Initializing\n");
> +
> +#if defined(CONFIG_DDR_DLL)
> + {
> + /*
> + * Work around to stabilize DDR DLL MSYNC_IN.
> + * Errata DDR9 seems to have been fixed.
> + * This is now the workaround for Errata DDR11:
> + * Override DLL = 1, Course Adj = 1, Tap Select = 0
> + */
> +
> + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
> +
> + gur->ddrdllcr = 0x81000000;
> + asm("sync;isync;msync");
> + udelay(200);
> + }
> +#endif
> +
> +#if defined(CONFIG_SPD_EEPROM)
> + dram_size = spd_sdram ();
> +#else
> + dram_size = fixed_sdram ();
> +#endif
> +
> +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
> + /*
> + * Initialize and enable DDR ECC.
> + */
> + ddr_enable_ecc(dram_size);
> +#endif
> + /*
> + * SDRAM Initialization
> + */
> + sdram_init();
> +
> + puts(" DDR: ");
> + return dram_size;
> +}
> +
> +/*
> + * Initialize Local Bus
> + */
> +void
> +local_bus_init(void)
> +{
> + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
> + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
> +
> + uint clkdiv;
> + uint lbc_hz;
> + sys_info_t sysinfo;
> +
> + get_sys_info(&sysinfo);
> + clkdiv = (lbc->lcrr & 0x0f) * 2;
> + lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
> +
> + gur->lbiuiplldcr1 = 0x00078080;
> + if (clkdiv == 16) {
> + gur->lbiuiplldcr0 = 0x7c0f1bf0;
> + } else if (clkdiv == 8) {
> + gur->lbiuiplldcr0 = 0x6c0f1bf0;
> + } else if (clkdiv == 4) {
> + gur->lbiuiplldcr0 = 0x5c0f1bf0;
> + }
> +
> + lbc->lcrr |= 0x00030000;
> +
> + asm("sync;isync;msync");
> +
> + lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
> + lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
> +}
> +
> +/*
> + * Initialize SDRAM memory on the Local Bus.
> + */
> +void
> +sdram_init(void)
> +{
> +#if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM)
> +
> + uint idx;
> + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
> + uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
> + uint lsdmr_common;
> +
> + puts(" SDRAM: ");
> +
> + print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
> +
> + /*
> + * Setup SDRAM Base and Option Registers
> + */
> + lbc->or3 = CFG_OR3_PRELIM;
> + asm("msync");
> +
> + lbc->br3 = CFG_BR3_PRELIM;
> + asm("msync");
> +
> + lbc->lbcr = CFG_LBC_LBCR;
> + asm("msync");
> +
> +
> + lbc->lsrt = CFG_LBC_LSRT;
> + lbc->mrtpr = CFG_LBC_MRTPR;
> + asm("msync");
> +
> + /*
> + * MPC8548 uses "new" 15-16 style addressing.
> + */
> + lsdmr_common = CFG_LBC_LSDMR_COMMON;
> + lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
> +
> + /*
> + * Issue PRECHARGE ALL command.
> + */
> + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
> + asm("sync;msync");
> + *sdram_addr = 0xff;
> + ppcDcbf((unsigned long) sdram_addr);
> + udelay(100);
> +
> + /*
> + * Issue 8 AUTO REFRESH commands.
> + */
> + for (idx = 0; idx < 8; idx++) {
> + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
> + asm("sync;msync");
> + *sdram_addr = 0xff;
> + ppcDcbf((unsigned long) sdram_addr);
> + udelay(100);
> + }
> +
> + /*
> + * Issue 8 MODE-set command.
> + */
> + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
> + asm("sync;msync");
> + *sdram_addr = 0xff;
> + ppcDcbf((unsigned long) sdram_addr);
> + udelay(100);
> +
> + /*
> + * Issue NORMAL OP command.
> + */
> + lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
> + asm("sync;msync");
> + *sdram_addr = 0xff;
> + ppcDcbf((unsigned long) sdram_addr);
> + udelay(200); /* Overkill. Must wait > 200 bus cycles */
> +
> +#endif /* enable SDRAM init */
> +}
> +
> +#if defined(CFG_DRAM_TEST)
> +int
> +testdram(void)
> +{
> + uint *pstart = (uint *) CFG_MEMTEST_START;
> + uint *pend = (uint *) CFG_MEMTEST_END;
> + uint *p;
> +
> + printf("Testing DRAM from 0x%08x to 0x%08x\n",
> + CFG_MEMTEST_START,
> + CFG_MEMTEST_END);
> +
> + printf("DRAM test phase 1:\n");
> + for (p = pstart; p < pend; p++)
> + *p = 0xaaaaaaaa;
> +
> + for (p = pstart; p < pend; p++) {
> + if (*p != 0xaaaaaaaa) {
> + printf ("DRAM test fails at: %08x\n", (uint) p);
> + return 1;
> + }
> + }
> +
> + printf("DRAM test phase 2:\n");
> + for (p = pstart; p < pend; p++)
> + *p = 0x55555555;
> +
> + for (p = pstart; p < pend; p++) {
> + if (*p != 0x55555555) {
> + printf ("DRAM test fails at: %08x\n", (uint) p);
> + return 1;
> + }
> + }
> +
> + printf("DRAM test passed.\n");
> + return 0;
> +}
> +#endif
> +
> +#if !defined(CONFIG_SPD_EEPROM)
> +/*************************************************************************
> + * fixed_sdram init -- doesn't use serial presence detect.
> + * assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
> + ************************************************************************/
> +long int fixed_sdram (void)
> +{
> + #define CFG_DDR_CONTROL 0xc300c000
> +
> + volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR);
> +
> + ddr->cs0_bnds = 0x0000007f;
> + ddr->cs1_bnds = 0x008000ff;
> + ddr->cs2_bnds = 0x00000000;
> + ddr->cs3_bnds = 0x00000000;
> + ddr->cs0_config = 0x80010101;
> + ddr->cs1_config = 0x80010101;
> + ddr->cs2_config = 0x00000000;
> + ddr->cs3_config = 0x00000000;
> + ddr->ext_refrec = 0x00000000;
> + ddr->timing_cfg_0 = 0x00220802;
> + ddr->timing_cfg_1 = 0x38377322;
> + ddr->timing_cfg_2 = 0x0fa044C7;
> + ddr->sdram_cfg = 0x4300C000;
> + ddr->sdram_cfg_2 = 0x24401000;
> + ddr->sdram_mode = 0x23C00542;
> + ddr->sdram_mode_2 = 0x00000000;
> + ddr->sdram_interval = 0x05080100;
> + ddr->sdram_md_cntl = 0x00000000;
> + ddr->sdram_data_init = 0x00000000;
> + ddr->sdram_clk_cntl = 0x03800000;
> + asm("sync;isync;msync");
> + udelay(500);
> +
> + #if defined (CONFIG_DDR_ECC)
> + /* Enable ECC checking */
> + ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
> + #else
> + ddr->sdram_cfg = CFG_DDR_CONTROL;
> + #endif
> +
> + return CFG_SDRAM_SIZE * 1024 * 1024;
> +}
> +#endif
> +
> +#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
> +/* For some reason the Tundra PCI bridge shows up on itself as a
> + * different device. Work around that by refusing to configure it.
> + */
> +void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
> +
> +static struct pci_config_table pci_sbc8548_config_table[] = {
> + {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
> + {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
> + {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
> + mpc85xx_config_via_usbide, {0,0,0}},
> + {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
> + mpc85xx_config_via_usb, {0,0,0}},
> + {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
> + mpc85xx_config_via_usb2, {0,0,0}},
> + {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
> + mpc85xx_config_via_power, {0,0,0}},
> + {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
> + mpc85xx_config_via_ac97, {0,0,0}},
> + {},
> +};
> +
> +static struct pci_controller pci1_hose = {
> + config_table: pci_sbc8548_config_table};
> +#endif /* CONFIG_PCI */
> +
> +#ifdef CONFIG_PCI2
> +static struct pci_controller pci2_hose;
> +#endif /* CONFIG_PCI2 */
> +
> +#ifdef CONFIG_PCIE1
> +static struct pci_controller pcie1_hose;
> +#endif /* CONFIG_PCIE1 */
> +
> +int first_free_busno=0;
> +
> +void
> +pci_init_board(void)
> +{
> + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
> +
> +#ifdef CONFIG_PCI1
> +{
> + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
> + extern void fsl_pci_init(struct pci_controller *hose);
> + struct pci_controller *hose = &pci1_hose;
> + struct pci_config_table *table;
> +
> + uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
> + uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
> + uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
> +
> + uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6);
> +
> + uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
> +
> + if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
> + printf (" PCI: %d bit, %s MHz, %s, %s, %s\n",
> + (pci_32) ? 32 : 64,
> + (pci_speed == 33333000) ? "33" :
> + (pci_speed == 66666000) ? "66" : "unknown",
> + pci_clk_sel ? "sync" : "async",
> + pci_agent ? "agent" : "host",
> + pci_arb ? "arbiter" : "external-arbiter"
> + );
> +
> +
> + /* inbound */
> + pci_set_region(hose->regions + 0,
> + CFG_PCI_MEMORY_BUS,
> + CFG_PCI_MEMORY_PHYS,
> + CFG_PCI_MEMORY_SIZE,
> + PCI_REGION_MEM | PCI_REGION_MEMORY);
> +
> +
> + /* outbound memory */
> + pci_set_region(hose->regions + 1,
> + CFG_PCI1_MEM_BASE,
> + CFG_PCI1_MEM_PHYS,
> + CFG_PCI1_MEM_SIZE,
> + PCI_REGION_MEM);
> +
> + /* outbound io */
> + pci_set_region(hose->regions + 2,
> + CFG_PCI1_IO_BASE,
> + CFG_PCI1_IO_PHYS,
> + CFG_PCI1_IO_SIZE,
> + PCI_REGION_IO);
> + hose->region_count = 3;
> +
> + /* relocate config table pointers */
> + hose->config_table = \
> + (struct pci_config_table *)((uint)hose->config_table + gd->reloc_off);
> + for (table = hose->config_table; table && table->vendor; table++)
> + table->config_device += gd->reloc_off;
> +
> + hose->first_busno=first_free_busno;
> + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
> +
> + fsl_pci_init(hose);
> + first_free_busno=hose->last_busno+1;
> + printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
> +#ifdef CONFIG_PCIX_CHECK
> + if (!(gur->pordevsr & PORDEVSR_PCI)) {
> + /* PCI-X init */
> + if (CONFIG_SYS_CLK_FREQ < 66000000)
> + printf("PCI-X will only work at 66 MHz\n");
> +
> + reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
> + | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
> + pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
> + }
> +#endif
> + } else {
> + printf (" PCI: disabled\n");
> + }
> +}
> +#else
> + gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
> +#endif
> +
> +#ifdef CONFIG_PCI2
> +{
> + uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
> + uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
> + if (pci_dual) {
> + printf (" PCI2: 32 bit, 66 MHz, %s\n",
> + pci2_clk_sel ? "sync" : "async");
> + } else {
> + printf (" PCI2: disabled\n");
> + }
> +}
> +#else
> + gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */
> +#endif /* CONFIG_PCI2 */
> +
> +#ifdef CONFIG_PCIE1
> +{
> + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
> + extern void fsl_pci_init(struct pci_controller *hose);
> + struct pci_controller *hose = &pcie1_hose;
> + int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
> +
> + int pcie_configured = io_sel >= 1;
> +
> + if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
> + printf ("\n PCIE connected to slot as %s (base address %x)",
> + pcie_ep ? "End Point" : "Root Complex",
> + (uint)pci);
> +
> + if (pci->pme_msg_det) {
> + pci->pme_msg_det = 0xffffffff;
> + debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
> + }
> + printf ("\n");
> +
> + /* inbound */
> + pci_set_region(hose->regions + 0,
> + CFG_PCI_MEMORY_BUS,
> + CFG_PCI_MEMORY_PHYS,
> + CFG_PCI_MEMORY_SIZE,
> + PCI_REGION_MEM | PCI_REGION_MEMORY);
> +
> + /* outbound memory */
> + pci_set_region(hose->regions + 1,
> + CFG_PCIE1_MEM_BASE,
> + CFG_PCIE1_MEM_PHYS,
> + CFG_PCIE1_MEM_SIZE,
> + PCI_REGION_MEM);
> +
> + /* outbound io */
> + pci_set_region(hose->regions + 2,
> + CFG_PCIE1_IO_BASE,
> + CFG_PCIE1_IO_PHYS,
> + CFG_PCIE1_IO_SIZE,
> + PCI_REGION_IO);
> +
> + hose->region_count = 3;
> +
> + hose->first_busno=first_free_busno;
> + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
> +
> + fsl_pci_init(hose);
> + printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno);
> +
> + first_free_busno=hose->last_busno+1;
> +
> + } else {
> + printf (" PCIE: disabled\n");
> + }
> + }
> +#else
> + gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
> +#endif
> +
> +}
> +
> +int last_stage_init(void)
> +{
> + return 0;
> +}
> +
> +#if defined(CONFIG_OF_BOARD_SETUP)
> +void
> +ft_pci_setup(void *blob, bd_t *bd)
> +{
> + int node, tmp[2];
> + const char *path;
> +
> + node = fdt_path_offset(blob, "/aliases");
> + tmp[0] = 0;
> + if (node >= 0) {
> +#ifdef CONFIG_PCI1
> + path = fdt_getprop(blob, node, "pci0", NULL);
> + if (path) {
> + tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
> + do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
> + }
> +#endif
> +#ifdef CONFIG_PCIE1
> + path = fdt_getprop(blob, node, "pci1", NULL);
> + if (path) {
> + tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
> + do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
> + }
> +#endif
> + }
> +}
> +#endif
> +
> +#if defined(CONFIG_OF_BOARD_SETUP)
> +void
> +ft_board_setup(void *blob, bd_t *bd)
> +{
> + ft_cpu_setup(blob, bd);
> +#ifdef CONFIG_PCI
> + ft_pci_setup(blob, bd);
> +#endif
> +}
> +#endif
> +
>
>
>
>
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