[U-Boot-Users] U-Boot hangs when try to access PCI window beyond 256 MB using md command

[vivek.trivedi at wipro.com]

Hi ,
 
We are using U-Boot-1.1.3 on a custom MPC8349ADS board with 2 PCI buses
configured in Host mode.We have 256 MB DDR2 in our board.
 
We have connected 8 DSPs on PCI bus 1.
U-Boot is assigning base address for DSPs from 0x80000000 to 0x93800000.
 
We are able to access any location from 0x80000000 to 0x0x8FFFFFFF i.e
first 256 MB using md command in U-BOOT.
But when i try to access any location starting from 0x90000000 to
0x93800000(next 256 MB), U-Boot hangs :
 
=>md 0x90000000 
90000000: 
 
Even though PCI LAWBARs and Outbound window is configured for 512 MB
starting from 0x80000000.
 
I am not able to understand why i am not able to access any location
starting from 0x90000000.
Please help me in as i have already wasted too much time in debugging
this issue.
 
 
 
I am also attaching the U-Boot PCI settings:
 
We are Configuring PCI bus in Host mode with following settings:
/* PCI window setting in include/configs/MPC8349ADS.h  start */
#define CFG_PCI1_MEM_BASE 0x80000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */

#define CFG_PCI1_IO_BASE 0x00000000
#define CFG_PCI1_IO_PHYS 0xe2000000
#define CFG_PCI1_IO_SIZE 0x01000000 /* 16M */
/* PCI window setting in MPC8349ADS.h  start */
 
PCI LAWBARas setting:
 
/* PCI LAWBARs setting in cpu/83xx/pci.c : start*/
 pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;  /* base: 0x80000000
*/
 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
 
 pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;  /* base: 0xe2000000 */
 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M;
/* PCI LAWBARs setting in cpu/83xx/pci.c  :end*/
 
PCI Outbound translation register setting:
 /* PCI1 mem space  */
 pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
/* base: 0x80000000 */
 pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
/* base: 0x80000000 */
 pci_pot[0].pocmr = POCMR_EN | (POCMR_CM_512M & POCMR_CM_MASK); 
 
 /* PCI1 IO space */
 pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
 pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
 pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_16M &
POCMR_CM_MASK);

/*
  * Configure PCI Inbound Translation Windows
  */
 
 /* we need RAM mapped to PCI space for the devices to
  * access main memory */
 pci_ctrl[0].pitar1 = 0x0;
 pci_ctrl[0].pibar1 = 0x0;
 pci_ctrl[0].piebar1 = 0x0;
 pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);

 hose->first_busno = 0;
 hose->last_busno = 0xff;
 
 /* PCI memory space */
 pci_set_region(hose->regions + 0,
         CFG_PCI1_MEM_BASE,        /* base: 0x80000000 */
         CFG_PCI1_MEM_PHYS,
         CFG_PCI1_MEM_SIZE,         /* Size is 512 MB */
         PCI_REGION_MEM); 
 
 /* PCI IO space */
 pci_set_region(hose->regions + 1,
         CFG_PCI1_IO_BASE,
         CFG_PCI1_IO_PHYS,
         CFG_PCI1_IO_SIZE,
         PCI_REGION_IO);
 
 /* System memory space */
 pci_set_region(hose->regions + 2,
         CONFIG_PCI_SYS_MEM_BUS,
         CONFIG_PCI_SYS_MEM_PHYS,
         gd->ram_size, 
         PCI_REGION_MEM | PCI_REGION_MEMORY);
 
 hose->region_count = 3;
 

 pci_setup_indirect(hose,
      (CFG_IMMRBAR+0x8300),
      (CFG_IMMRBAR+0x8304));
 
 pci_register_hose(hose);
 
 /*
  * Write to Command register
  */
 reg16 = 0xff;
 dev = PCI_BDF(hose->first_busno, 0, 0);
 pci_hose_read_config_word (hose, dev, PCI_COMMAND, &reg16);
 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
 

 /*
  * Clear non-reserved bits in status register.
  */
 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
 
#ifdef CONFIG_PCI_SCAN_SHOW
 printf("PCI:   Bus Dev VenId DevId Class Int\n");
#endif
 /*
  * Hose scan.
  */
 hose->last_busno = pci_hose_scan(hose);

 
 
Thanks & Regards,
Vivek Trivedi
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