[U-Boot-Users] [PATCH 2/3] 83xx: serdes setup routines
Anton Vorontsov
avorontsov at ru.mvista.com
Thu Mar 13 14:44:50 CET 2008
On Wed, Mar 12, 2008 at 11:54:39PM +0100, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 18:07 Fri 07 Mar , Anton Vorontsov wrote:
> > This patch adds few routines to configure serdes on 837x targets.
> >
> > Signed-off-by: Anton Vorontsov <avorontsov at ru.mvista.com>
> > ---
> > cpu/mpc83xx/Makefile | 2 +-
> > cpu/mpc83xx/serdes.c | 161 ++++++++++++++++++++++++++++++++++++++++++++++++++
> > include/fsl_serdes.h | 25 ++++++++
> > 3 files changed, 187 insertions(+), 1 deletions(-)
> > create mode 100644 cpu/mpc83xx/serdes.c
> > create mode 100644 include/fsl_serdes.h
> >
> > diff --git a/cpu/mpc83xx/Makefile b/cpu/mpc83xx/Makefile
> > index 94a3cb8..678be29 100644
> > --- a/cpu/mpc83xx/Makefile
> > +++ b/cpu/mpc83xx/Makefile
> > @@ -29,7 +29,7 @@ LIB = $(obj)lib$(CPU).a
> >
> > START = start.o
> > COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \
> > - spd_sdram.o ecc.o qe_io.o pci.o fdt.o
> > + spd_sdram.o ecc.o qe_io.o pci.o fdt.o serdes.o
> Please split it with on line for one file
Not sure if just splitting COBJS in separate lines is any better.
In long term we should start using $(CONFIG_ symbols. I can start
doing it for serdes...
> >
[...]
> > +#ifdef CONFIG_FSL_SERDES
> Please move it to the Makefile
- - - -
From: Anton Vorontsov <avorontsov at ru.mvista.com>
Subject: 83xx: serdes setup routines
This patch adds few routines to configure serdes on 837x targets.
Signed-off-by: Anton Vorontsov <avorontsov at ru.mvista.com>
---
cpu/mpc83xx/Makefile | 6 +-
cpu/mpc83xx/serdes.c | 156 ++++++++++++++++++++++++++++++++++++++++++++++++++
include/fsl_serdes.h | 25 ++++++++
3 files changed, 185 insertions(+), 2 deletions(-)
create mode 100644 cpu/mpc83xx/serdes.c
create mode 100644 include/fsl_serdes.h
diff --git a/cpu/mpc83xx/Makefile b/cpu/mpc83xx/Makefile
index 94a3cb8..27e1567 100644
--- a/cpu/mpc83xx/Makefile
+++ b/cpu/mpc83xx/Makefile
@@ -28,8 +28,10 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(CPU).a
START = start.o
-COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \
- spd_sdram.o ecc.o qe_io.o pci.o fdt.o
+COBJS-y += traps.o cpu.o cpu_init.o speed.o interrupts.o \
+ spd_sdram.o ecc.o qe_io.o pci.o
+COBJS-$(CONFIG_FSL_SERDES) += serdes.o
+COBJS = $(COBJS-y)
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/cpu/mpc83xx/serdes.c b/cpu/mpc83xx/serdes.c
new file mode 100644
index 0000000..1b2bdd7
--- /dev/null
+++ b/cpu/mpc83xx/serdes.c
@@ -0,0 +1,156 @@
+/*
+ * Freescale SerDes initialization routine
+ *
+ * Copyright (C) 2007 Freescale Semicondutor, Inc. All rights reserved.
+ * Copyright (C) 2008 MontaVista Software, Inc. All rights reserved.
+ *
+ * Author: Li Yang <leoli at freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <fsl_serdes.h>
+
+/* SerDes registers */
+#define FSL_SRDSCR0_OFFS 0x0
+#define FSL_SRDSCR0_DPP_1V2 0x00008800
+#define FSL_SRDSCR1_OFFS 0x4
+#define FSL_SRDSCR1_PLLBW 0x00000040
+#define FSL_SRDSCR2_OFFS 0x8
+#define FSL_SRDSCR2_VDD_1V2 0x00800000
+#define FSL_SRDSCR2_SEIC_MASK 0x00001c1c
+#define FSL_SRDSCR2_SEIC_SATA 0x00001414
+#define FSL_SRDSCR2_SEIC_PEX 0x00001010
+#define FSL_SRDSCR2_SEIC_SGMII 0x00000101
+#define FSL_SRDSCR3_OFFS 0xc
+#define FSL_SRDSCR3_KFR_SATA 0x10100000
+#define FSL_SRDSCR3_KPH_SATA 0x04040000
+#define FSL_SRDSCR3_SDFM_SATA_PEX 0x01010000
+#define FSL_SRDSCR3_SDTXL_SATA 0x00000505
+#define FSL_SRDSCR4_OFFS 0x10
+#define FSL_SRDSCR4_PROT_SATA 0x00000808
+#define FSL_SRDSCR4_PROT_PEX 0x00000101
+#define FSL_SRDSCR4_PROT_SGMII 0x00000505
+#define FSL_SRDSCR4_PLANE_X2 0x01000000
+#define FSL_SRDSRSTCTL_OFFS 0x20
+#define FSL_SRDSRSTCTL_RST 0x80000000
+#define FSL_SRDSRSTCTL_SATA_RESET 0xf
+
+static void setup_serdes(void *regs, char proto, char rfcks, char vdd)
+{
+ u32 tmp;
+
+ /* 1.0V corevdd */
+ if (vdd) {
+ /* DPPE/DPPA = 0 */
+ tmp = in_be32(regs + FSL_SRDSCR0_OFFS);
+ tmp &= ~FSL_SRDSCR0_DPP_1V2;
+ out_be32(regs + FSL_SRDSCR0_OFFS, tmp);
+
+ /* VDD = 0 */
+ tmp = in_be32(regs + FSL_SRDSCR2_OFFS);
+ tmp &= ~FSL_SRDSCR2_VDD_1V2;
+ out_be32(regs + FSL_SRDSCR2_OFFS, tmp);
+ }
+
+ /* protocol specific configuration */
+ switch (proto) {
+ case FSL_SERDES_PROTO_SATA:
+ /* Set and clear reset bits */
+ tmp = in_be32(regs + FSL_SRDSRSTCTL_OFFS);
+ tmp |= FSL_SRDSRSTCTL_SATA_RESET;
+ out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp);
+ udelay(1000);
+ tmp &= ~FSL_SRDSRSTCTL_SATA_RESET;
+ out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp);
+
+ /* Configure SRDSCR1 */
+ tmp = in_be32(regs + FSL_SRDSCR1_OFFS);
+ tmp &= ~FSL_SRDSCR1_PLLBW;
+ out_be32(regs + FSL_SRDSCR1_OFFS, tmp);
+
+ /* Configure SRDSCR2 */
+ tmp = in_be32(regs + FSL_SRDSCR2_OFFS);
+ tmp &= ~FSL_SRDSCR2_SEIC_MASK;
+ tmp |= FSL_SRDSCR2_SEIC_SATA;
+ out_be32(regs + FSL_SRDSCR2_OFFS, tmp);
+
+ /* Configure SRDSCR3 */
+ tmp = FSL_SRDSCR3_KFR_SATA | FSL_SRDSCR3_KPH_SATA |
+ FSL_SRDSCR3_SDFM_SATA_PEX |
+ FSL_SRDSCR3_SDTXL_SATA;
+ out_be32(regs + FSL_SRDSCR3_OFFS, tmp);
+
+ /* Configure SRDSCR4 */
+ tmp = rfcks | FSL_SRDSCR4_PROT_SATA;
+ out_be32(regs + FSL_SRDSCR4_OFFS, tmp);
+ break;
+ case FSL_SERDES_PROTO_PEX:
+ case FSL_SERDES_PROTO_PEX_X2:
+ /* Configure SRDSCR1 */
+ tmp = in_be32(regs + FSL_SRDSCR1_OFFS);
+ tmp |= FSL_SRDSCR1_PLLBW;
+ out_be32(regs + FSL_SRDSCR1_OFFS, tmp);
+
+ /* Configure SRDSCR2 */
+ tmp = in_be32(regs + FSL_SRDSCR2_OFFS);
+ tmp &= ~FSL_SRDSCR2_SEIC_MASK;
+ tmp |= FSL_SRDSCR2_SEIC_PEX;
+ out_be32(regs + FSL_SRDSCR2_OFFS, tmp);
+
+ /* Configure SRDSCR3 */
+ tmp = FSL_SRDSCR3_SDFM_SATA_PEX;
+ out_be32(regs + FSL_SRDSCR3_OFFS, tmp);
+
+ /* Configure SRDSCR4 */
+ tmp = rfcks | FSL_SRDSCR4_PROT_PEX;
+ if (proto == FSL_SERDES_PROTO_PEX_X2)
+ tmp |= FSL_SRDSCR4_PLANE_X2;
+ out_be32(regs + FSL_SRDSCR4_OFFS, tmp);
+ break;
+ case FSL_SERDES_PROTO_SGMII:
+ /* Configure SRDSCR1 */
+ tmp = in_be32(regs + FSL_SRDSCR1_OFFS);
+ tmp &= ~FSL_SRDSCR1_PLLBW;
+ out_be32(regs + FSL_SRDSCR1_OFFS, tmp);
+
+ /* Configure SRDSCR2 */
+ tmp = in_be32(regs + FSL_SRDSCR2_OFFS);
+ tmp &= ~FSL_SRDSCR2_SEIC_MASK;
+ tmp |= FSL_SRDSCR2_SEIC_SGMII;
+ out_be32(regs + FSL_SRDSCR2_OFFS, tmp);
+
+ /* Configure SRDSCR3 */
+ out_be32(regs + FSL_SRDSCR3_OFFS, 0);
+
+ /* Configure SRDSCR4 */
+ tmp = rfcks | FSL_SRDSCR4_PROT_SGMII;
+ out_be32(regs + FSL_SRDSCR4_OFFS, tmp);
+ break;
+ default:
+ return;
+ }
+
+ /* Do a software reset */
+ tmp = in_be32(regs + FSL_SRDSRSTCTL_OFFS);
+ tmp |= FSL_SRDSRSTCTL_RST;
+ out_be32(regs + FSL_SRDSRSTCTL_OFFS, tmp);
+}
+
+void fsl_setup_serdes(void)
+{
+#ifdef CONFIG_FSL_SERDES1
+ setup_serdes((void *)CONFIG_FSL_SERDES1, CONFIG_FSL_SERDES1_PROTO,
+ CONFIG_FSL_SERDES1_CLK, CONFIG_FSL_SERDES1_VDD_1V);
+#endif
+#ifdef CONFIG_FSL_SERDES2
+ setup_serdes((void *)CONFIG_FSL_SERDES2, CONFIG_FSL_SERDES2_PROTO,
+ CONFIG_FSL_SERDES2_CLK, CONFIG_FSL_SERDES2_VDD_1V);
+#endif
+}
diff --git a/include/fsl_serdes.h b/include/fsl_serdes.h
new file mode 100644
index 0000000..4c9a766
--- /dev/null
+++ b/include/fsl_serdes.h
@@ -0,0 +1,25 @@
+#ifndef __FSL_SERDES_H
+#define __FSL_SERDES_H
+
+#include <config.h>
+
+#ifdef CONFIG_FSL_SERDES
+
+#define FSL_SERDES_CLK_100 0
+#define FSL_SERDES_CLK_125 1
+#define FSL_SERDES_CLK_150 3
+#define FSL_SERDES_PROTO_SATA 0
+#define FSL_SERDES_PROTO_PEX 1
+#define FSL_SERDES_PROTO_PEX_X2 2
+#define FSL_SERDES_PROTO_SGMII 3
+#define FSL_SERDES_VDD1V 1
+
+extern void fsl_setup_serdes(void);
+
+#else
+
+static inline void fsl_setup_serdes(void) {}
+
+#endif
+
+#endif /* __FSL_SERDES_H */
--
1.5.2.2
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