[U-Boot-Users] [MIPS] Implement flush_cache()

[Andrew Dyer]

On Tue, Mar 18, 2008 at 11:42 AM, Shinya Kuribayashi
<skuribay at ruby.dti.ne.jp> wrote:
> Signed-off-by: Shinya Kuribayashi <skuribay at ruby.dti.ne.jp>
>  ---
>  +       while (1) {
>  +               cache_op(Hit_Writeback_Inv_D, start_addr);
>  +               if (addr == aend)
>  +                       break;
>  +               addr += lsize;
>  +       }

looking at how cache_flush() is used (see common/cmd_load.c,
common/cmd_elf.c, etc), I believe this loop should also do a cache_op
with Hit_Invalidate_I to invalidate the icache.

seems like it would be easier to read if the condition was included in
the while() statement


-- 
Hardware, n.:
 The parts of a computer system that can be kicked.