[U-Boot] [PATCH 04/13 v5] ARM: OMAP3: Add lowlevel init and sys_info common files

dirk.behme at googlemail.com dirk.behme at googlemail.com
Sun Nov 2 19:36:27 CET 2008


Subject: [PATCH 04/13 v5] ARM: OMAP3: Add lowlevel init and sys_info common files

From: Dirk Behme <dirk.behme at gmail.com>

Add assembly lowlevel init and sys_info common files

Signed-off-by: Dirk Behme <dirk.behme at gmail.com>

---

Changes in version v3:
- Add detection and support for 128MB/256MB RAM by Mans Rullgard

Changes in version v2:

- Move common ARM Cortex A8 code to cpu/arm_cortexa8/ and OMAP3 SoC specific common code to cpu/arm_cortexa8/omap3 as proposed by Wolfgang.

 cpu/arm_cortexa8/omap3/Makefile        |   46 ++++
 cpu/arm_cortexa8/omap3/config.mk       |   36 +++
 cpu/arm_cortexa8/omap3/lowlevel_init.S |  359 +++++++++++++++++++++++++++++++++
 cpu/arm_cortexa8/omap3/sys_info.c      |  334 ++++++++++++++++++++++++++++++
 4 files changed, 775 insertions(+)

Index: u-boot-main/cpu/arm_cortexa8/omap3/Makefile
===================================================================
--- /dev/null
+++ u-boot-main/cpu/arm_cortexa8/omap3/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	=  $(obj)lib$(SOC).a
+
+SOBJS	:= lowlevel_init.o
+COBJS	:= sys_info.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+all:	 $(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
Index: u-boot-main/cpu/arm_cortexa8/omap3/config.mk
===================================================================
--- /dev/null
+++ u-boot-main/cpu/arm_cortexa8/omap3/config.mk
@@ -0,0 +1,36 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <gj at denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
+		     -msoft-float
+
+# Make ARMv5 to allow more compilers to work, even though its v7a.
+PLATFORM_CPPFLAGS += -march=armv5
+# =========================================================================
+#
+# Supply options according to compiler version
+#
+# =========================================================================
+PLATFORM_CPPFLAGS +=$(call cc-option)
+PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,)
+PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,\
+		    $(call cc-option,-malignment-traps,))
Index: u-boot-main/cpu/arm_cortexa8/omap3/lowlevel_init.S
===================================================================
--- /dev/null
+++ u-boot-main/cpu/arm_cortexa8/omap3/lowlevel_init.S
@@ -0,0 +1,359 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Initial Code by:
+ * Richard Woodruff <r-woodruff2 at ti.com>
+ * Syed Mohammed Khasim <khasim at ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/clocks_omap3.h>
+
+_TEXT_BASE:
+	.word	TEXT_BASE	/* sdram load addr from config.mk */
+
+#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT)
+/**************************************************************************
+ * cpy_clk_code: relocates clock code into SRAM where its safer to execute
+ * R1 = SRAM destination address.
+ *************************************************************************/
+.global cpy_clk_code
+ cpy_clk_code:
+	/* Copy DPLL code into SRAM */
+	adr	r0, go_to_speed		/* get addr of clock setting code */
+	mov	r2, #384		/* r2 size to copy (div by 32 bytes) */
+	mov	r1, r1			/* r1 <- dest address (passed in) */
+	add	r2, r2, r0		/* r2 <- source end address */
+next2:
+	ldmia	r0!, {r3 - r10}		/* copy from source address [r0] */
+	stmia	r1!, {r3 - r10}		/* copy to   target address [r1] */
+	cmp	r0, r2			/* until source end address [r2] */
+	bne	next2
+	mov	pc, lr			/* back to caller */
+
+/* ***************************************************************************
+ *  go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
+ *               -executed from SRAM.
+ *  R0 = CM_CLKEN_PLL-bypass value
+ *  R1 = CM_CLKSEL1_PLL-m, n, and divider values
+ *  R2 = CM_CLKSEL_CORE-divider values
+ *  R3 = CM_IDLEST_CKGEN - addr dpll lock wait
+ *
+ *  Note: If core unlocks/relocks and SDRAM is running fast already it gets
+ *        confused.  A reset of the controller gets it back.  Taking away its
+ *        L3 when its not in self refresh seems bad for it.  Normally, this
+ *	  code runs from flash before SDR is init so that should be ok.
+ ****************************************************************************/
+.global go_to_speed
+ go_to_speed:
+	stmfd sp!, {r4 - r6}
+
+	/* move into fast relock bypass */
+	ldr	r4, pll_ctl_add
+	str	r0, [r4]
+wait1:
+	ldr	r5, [r3]		/* get status */
+	and	r5, r5, #0x1		/* isolate core status */
+	cmp	r5, #0x1		/* still locked? */
+	beq	wait1			/* if lock, loop */
+
+	/* set new dpll dividers _after_ in bypass */
+	ldr	r5, pll_div_add1
+	str	r1, [r5]		/* set m, n, m2 */
+	ldr	r5, pll_div_add2
+	str	r2, [r5]		/* set l3/l4/.. dividers*/
+	ldr	r5, pll_div_add3	/* wkup */
+	ldr	r2, pll_div_val3	/* rsm val */
+	str	r2, [r5]
+	ldr	r5, pll_div_add4	/* gfx */
+	ldr	r2, pll_div_val4
+	str	r2, [r5]
+	ldr	r5, pll_div_add5	/* emu */
+	ldr	r2, pll_div_val5
+	str	r2, [r5]
+
+	/* now prepare GPMC (flash) for new dpll speed */
+	/* flash needs to be stable when we jump back to it */
+	ldr	r5, flash_cfg3_addr
+	ldr	r2, flash_cfg3_val
+	str	r2, [r5]
+	ldr	r5, flash_cfg4_addr
+	ldr	r2, flash_cfg4_val
+	str	r2, [r5]
+	ldr	r5, flash_cfg5_addr
+	ldr	r2, flash_cfg5_val
+	str	r2, [r5]
+	ldr	r5, flash_cfg1_addr
+	ldr	r2, [r5]
+	orr	r2, r2, #0x3		/* up gpmc divider */
+	str	r2, [r5]
+
+	/* lock DPLL3 and wait a bit */
+	orr	r0, r0, #0x7	/* set up for lock mode */
+	str	r0, [r4]	/* lock */
+	nop			/* ARM slow at this point working at sys_clk */
+	nop
+	nop
+	nop
+wait2:
+	ldr	r5, [r3]	/* get status */
+	and	r5, r5, #0x1	/* isolate core status */
+	cmp	r5, #0x1	/* still locked? */
+	bne	wait2		/* if lock, loop */
+	nop
+	nop
+	nop
+	nop
+	ldmfd sp!, {r4 - r6}
+	mov	pc, lr		/* back to caller, locked */
+
+_go_to_speed: .word go_to_speed
+
+/* these constants need to be close for PIC code */
+/* The Nor has to be in the Flash Base CS0 for this condition to happen */
+flash_cfg1_addr:
+	.word (GPMC_CONFIG_CS0 + GPMC_CONFIG1)
+flash_cfg3_addr:
+	.word (GPMC_CONFIG_CS0 + GPMC_CONFIG3)
+flash_cfg3_val:
+	.word STNOR_GPMC_CONFIG3
+flash_cfg4_addr:
+	.word (GPMC_CONFIG_CS0 + GPMC_CONFIG4)
+flash_cfg4_val:
+	.word STNOR_GPMC_CONFIG4
+flash_cfg5_val:
+	.word STNOR_GPMC_CONFIG5
+flash_cfg5_addr:
+	.word (GPMC_CONFIG_CS0 + GPMC_CONFIG5)
+pll_ctl_add:
+	.word CM_CLKEN_PLL
+pll_div_add1:
+	.word CM_CLKSEL1_PLL
+pll_div_add2:
+	.word CM_CLKSEL_CORE
+pll_div_add3:
+	.word CM_CLKSEL_WKUP
+pll_div_val3:
+	.word (WKUP_RSM << 1)
+pll_div_add4:
+	.word CM_CLKSEL_GFX
+pll_div_val4:
+	.word (GFX_DIV << 0)
+pll_div_add5:
+	.word CM_CLKSEL1_EMU
+pll_div_val5:
+	.word CLSEL1_EMU_VAL
+
+#endif
+
+.globl lowlevel_init
+lowlevel_init:
+	ldr	sp,	SRAM_STACK
+	str	ip,	[sp]	/* stash old link register */
+	mov	ip,	lr	/* save link reg across call */
+	bl	 s_init		/* go setup pll,mux,memory */
+	ldr	ip,	[sp]	/* restore save ip */
+	mov	lr,	ip	/* restore link reg */
+
+	/* back to arch calling code */
+	mov	pc,	lr
+
+	/* the literal pools origin */
+	.ltorg
+
+REG_CONTROL_STATUS:
+	.word CONTROL_STATUS
+SRAM_STACK:
+	.word LOW_LEVEL_SRAM_STACK
+
+/* DPLL(1-4) PARAM TABLES */
+/* Each of the tables has M, N, FREQSEL, M2 values defined for nominal
+ * OPP (1.2V). The fields are defined according to dpll_param struct (clock.c).
+ * The values are defined for all possible sysclk and for ES1 and ES2.
+ */
+
+mpu_dpll_param:
+/* 12MHz */
+/* ES1 */
+.word 0x0FE, 0x07, 0x05, 0x01
+/* ES2 */
+.word 0x0FA, 0x05, 0x07, 0x01
+/* 3410 */
+.word 0x085, 0x05, 0x07, 0x01
+
+/* 13MHz */
+/* ES1 */
+.word 0x17D, 0x0C, 0x03, 0x01
+/* ES2 */
+.word 0x1F4, 0x0C, 0x03, 0x01
+/* 3410 */
+.word 0x10A, 0x0C, 0x03, 0x01
+
+/* 19.2MHz */
+/* ES1 */
+.word 0x179, 0x12, 0x04, 0x01
+/* ES2 */
+.word 0x271, 0x17, 0x03, 0x01
+/* 3410 */
+.word 0x14C, 0x17, 0x03, 0x01
+
+/* 26MHz */
+/* ES1 */
+.word 0x17D, 0x19, 0x03, 0x01
+/* ES2 */
+.word 0x0FA, 0x0C, 0x07, 0x01
+/* 3410 */
+.word 0x085, 0x0C, 0x07, 0x01
+
+/* 38.4MHz */
+/* ES1 */
+.word 0x1FA, 0x32, 0x03, 0x01
+/* ES2 */
+.word 0x271, 0x2F, 0x03, 0x01
+/* 3410 */
+.word 0x14C, 0x2F, 0x03, 0x01
+
+
+.globl get_mpu_dpll_param
+get_mpu_dpll_param:
+	adr r0, mpu_dpll_param
+	mov pc, lr
+
+iva_dpll_param:
+/* 12MHz */
+/* ES1 */
+.word 0x07D, 0x05, 0x07, 0x01
+/* ES2 */
+.word 0x0B4, 0x05, 0x07, 0x01
+/* 3410 */
+.word 0x085, 0x05, 0x07, 0x01
+
+/* 13MHz */
+/* ES1 */
+.word 0x0FA, 0x0C, 0x03, 0x01
+/* ES2 */
+.word 0x168, 0x0C, 0x03, 0x01
+/* 3410 */
+.word 0x10A, 0x0C, 0x03, 0x01
+
+/* 19.2MHz */
+/* ES1 */
+.word 0x082, 0x09, 0x07, 0x01
+/* ES2 */
+.word 0x0E1, 0x0B, 0x06, 0x01
+/* 3410 */
+.word 0x14C, 0x17, 0x03, 0x01
+
+/* 26MHz */
+/* ES1 */
+.word 0x07D, 0x0C, 0x07, 0x01
+/* ES2 */
+.word 0x0B4, 0x0C, 0x07, 0x01
+/* 3410 */
+.word 0x085, 0x0C, 0x07, 0x01
+
+/* 38.4MHz */
+/* ES1 */
+.word 0x13F, 0x30, 0x03, 0x01
+/* ES2 */
+.word 0x0E1, 0x17, 0x06, 0x01
+/* 3410 */
+.word 0x14C, 0x2F, 0x03, 0x01
+
+
+.globl get_iva_dpll_param
+get_iva_dpll_param:
+	adr r0, iva_dpll_param
+	mov pc, lr
+
+/* Core DPLL targets for L3 at 166 & L133 */
+core_dpll_param:
+/* 12MHz */
+/* ES1 */
+.word M_12_ES1, M_12_ES1, FSL_12_ES1, M2_12_ES1
+/* ES2 */
+.word M_12, N_12, FSEL_12, M2_12
+/* 3410 */
+.word M_12, N_12, FSEL_12, M2_12
+
+/* 13MHz */
+/* ES1 */
+.word M_13_ES1, N_13_ES1, FSL_13_ES1, M2_13_ES1
+/* ES2 */
+.word M_13,N_13,FSEL_13,M2_13
+/* 3410 */
+.word M_13,N_13,FSEL_13,M2_13
+
+/* 19.2MHz */
+/* ES1 */
+.word M_19p2_ES1, N_19p2_ES1, FSL_19p2_ES1, M2_19p2_ES1
+/* ES2 */
+.word M_19p2, N_19p2, FSEL_19p2, M2_19p2
+/* 3410 */
+.word M_19p2, N_19p2, FSEL_19p2, M2_19p2
+
+/* 26MHz */
+/* ES1 */
+.word M_26_ES1, N_26_ES1, FSL_26_ES1, M2_26_ES1
+/* ES2 */
+.word M_26, N_26, FSEL_26, M2_26
+/* 3410 */
+.word M_26, N_26, FSEL_26, M2_26
+
+/* 38.4MHz */
+/* ES1 */
+.word M_38p4_ES1, N_38p4_ES1, FSL_38p4_ES1, M2_38p4_ES1
+/* ES2 */
+.word M_38p4, N_38p4, FSEL_38p4, M2_38p4
+/* 3410 */
+.word M_38p4, N_38p4, FSEL_38p4, M2_38p4
+
+.globl get_core_dpll_param
+get_core_dpll_param:
+	adr r0, core_dpll_param
+	mov pc, lr
+
+/* PER DPLL values are same for both ES1 and ES2 */
+per_dpll_param:
+/* 12MHz */
+.word 0xD8, 0x05, 0x07, 0x09
+
+/* 13MHz */
+.word 0x1B0, 0x0C, 0x03, 0x09
+
+/* 19.2MHz */
+.word 0xE1, 0x09, 0x07, 0x09
+
+/* 26MHz */
+.word 0xD8, 0x0C, 0x07, 0x09
+
+/* 38.4MHz */
+.word 0xE1, 0x13, 0x07, 0x09
+
+.globl get_per_dpll_param
+get_per_dpll_param:
+	adr r0, per_dpll_param
+	mov pc, lr
Index: u-boot-main/cpu/arm_cortexa8/omap3/sys_info.c
===================================================================
--- /dev/null
+++ u-boot-main/cpu/arm_cortexa8/omap3/sys_info.c
@@ -0,0 +1,334 @@
+/*
+ * (C) Copyright 2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ *      Manikandan Pillai <mani.pillai at ti.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ *      Richard Woodruff <r-woodruff2 at ti.com>
+ *      Syed Mohammed Khasim <khasim at ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/mem.h>	/* get mem tables */
+#include <asm/arch/sys_proto.h>
+#include <i2c.h>
+
+extern omap3_sysinfo sysinfo;
+static u32 *gpmc_base = (u32 *)GPMC_BASE;
+
+/**************************************************************************
+ * get_gpmc0_type()
+ ***************************************************************************/
+u32 get_gpmc0_type(void)
+{
+#if defined(CONFIG_ENV_IS_IN_ONENAND)
+	return 1; /* OneNAND */
+#else
+	return 2; /* NAND */
+#endif
+}
+
+/****************************************************
+ * get_cpu_type() - low level get cpu type
+ * - no C globals yet.
+ ****************************************************/
+u32 get_cpu_type(void)
+{
+	/* fixme, need to get register defines for OMAP3 */
+	return CPU_3430;
+}
+
+/******************************************
+ * get_cpu_rev(void) - extract version info
+ ******************************************/
+u32 get_cpu_rev(void)
+{
+	u32 cpuid = 0;
+	/* On ES1.0 the IDCODE register is not exposed on L4
+	 * so using CPU ID to differentiate
+	 * between ES2.0 and ES1.0.
+	 */
+	__asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid));
+	if ((cpuid & 0xf) == 0x0)
+		return CPU_3430_ES1;
+	else
+		return CPU_3430_ES2;
+
+}
+
+/****************************************************
+ * is_mem_sdr() - return 1 if mem type in use is SDR
+ ****************************************************/
+u32 is_mem_sdr(void)
+{
+	volatile u32 *burst = (volatile u32 *) (SDRC_MR_0 + SDRC_CS0_OSET);
+	if (*burst == SDP_SDRC_MR_0_SDR)
+		return 1;
+	return 0;
+}
+
+/***********************************************************
+ * get_mem_type() - identify type of mDDR part used.
+ ***********************************************************/
+u32 get_mem_type(void)
+{
+#if defined(CONFIG_OMAP3_BEAGLE) || defined(CONFIG_OVERO)
+	return DDR_STACKED;
+#else
+	return DDR_DISCRETE;
+#endif
+}
+
+/***********************************************************************
+ * get_cs0_size() - get size of chip select 0/1
+ ************************************************************************/
+u32 get_sdr_cs_size(u32 offset)
+{
+	u32 size;
+
+	/* get ram size field */
+	size = readl(SDRC_MCFG_0 + offset) >> 8;
+	size &= 0x3FF;		/* remove unwanted bits */
+	size *= SZ_2M;		/* find size in MB */
+	return size;
+}
+
+/***********************************************************************
+ * get_sdr_cs_offset() - get offset of cs from cs0 start
+ ************************************************************************/
+u32 get_sdr_cs_offset(u32 cs)
+{
+	u32 offset;
+
+	if (!cs)
+		return 0;
+
+	offset = readl(SDRC_CS_CFG);
+	offset = (offset & 15) << 27 | (offset & 0x30) >> 17;
+
+	return offset;
+}
+
+/***********************************************************************
+ * get_board_type() - get board type based on current production stats.
+ *  - NOTE-1-: 2 I2C EEPROMs will someday be populated with proper info.
+ *    when they are available we can get info from there.  This should
+ *    be correct of all known boards up until today.
+ *  - NOTE-2- EEPROMs are populated but they are updated very slowly.  To
+ *    avoid waiting on them we will use ES version of the chip to get info.
+ *    A later version of the FPGA migth solve their speed issue.
+ ************************************************************************/
+u32 get_board_type(void)
+{
+	if (get_cpu_rev() == CPU_3430_ES2)
+		return sysinfo.board_type_v2;
+	else
+		return sysinfo.board_type_v1;
+}
+
+/******************************************************************
+ * get_sysboot_value() - get init word settings
+ ******************************************************************/
+inline u32 get_sysboot_value(void)
+{
+	return 0x0000003F & readl(CONTROL_STATUS);
+}
+
+/***************************************************************************
+ *  get_gpmc0_base() - Return current address hardware will be
+ *     fetching from. The below effectively gives what is correct, its a bit
+ *   mis-leading compared to the TRM.  For the most general case the mask
+ *   needs to be also taken into account this does work in practice.
+ *   - for u-boot we currently map:
+ *       -- 0 to nothing,
+ *       -- 4 to flash
+ *       -- 8 to enent
+ *       -- c to wifi
+ ****************************************************************************/
+u32 get_gpmc0_base(void)
+{
+	u32 b;
+
+	b = readl(gpmc_base + OFFS(GPMC_CONFIG7));
+	b &= 0x1F;		/* keep base [5:0] */
+	b = b << 24;		/* ret 0x0b000000 */
+	return b;
+}
+
+/*******************************************************************
+ * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand)
+ *******************************************************************/
+u32 get_gpmc0_width(void)
+{
+	return WIDTH_16BIT;
+}
+
+/*************************************************************************
+ * get_board_rev() - setup to pass kernel board revision information
+ * returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
+ *************************************************************************/
+u32 get_board_rev(void)
+{
+	return 0x20;
+}
+
+/*********************************************************************
+ *  display_board_info() - print banner with board info.
+ *********************************************************************/
+void display_board_info(u32 btype)
+{
+	char *bootmode[] = {
+		"NOR",
+		"ONENAND",
+		"NAND",
+		"P2a",
+		"NOR",
+		"NOR",
+		"P2a",
+		"P2b",
+	};
+	u32 brev = get_board_rev();
+	char db_ver[] = "0.0";	/* board type */
+	char mem_sdr[] = "mSDR";	/* memory type */
+	char mem_ddr[] = "LPDDR";
+	char t_tst[] = "TST";	/* security level */
+	char t_emu[] = "EMU";
+	char t_hs[] = "HS";
+	char t_gp[] = "GP";
+	char unk[] = "?";
+#ifdef CONFIG_LED_INFO
+	char led_string[CONFIG_LED_LEN] = { 0 };
+#endif
+	char p_l3[] = "165";
+	char p_cpu[] = "2";
+
+	char *db_s, *mem_s, *sec_s;
+	u32 cpu, rev, sec;
+
+	rev = get_cpu_rev();
+	cpu = get_cpu_type();
+	sec = get_device_type();
+
+	if (is_mem_sdr())
+		mem_s = mem_sdr;
+	else
+		mem_s = mem_ddr;
+
+	db_s = db_ver;
+	db_s[0] += (brev >> 4) & 0xF;
+	db_s[2] += brev & 0xF;
+
+	switch (sec) {
+	case TST_DEVICE:
+		sec_s = t_tst;
+		break;
+	case EMU_DEVICE:
+		sec_s = t_emu;
+		break;
+	case HS_DEVICE:
+		sec_s = t_hs;
+		break;
+	case GP_DEVICE:
+		sec_s = t_gp;
+		break;
+	default:
+		sec_s = unk;
+	}
+
+	printf("OMAP%s-%s rev %d, CPU-OPP%s L3-%sMHz\n", sysinfo.cpu_string,
+	       sec_s, rev, p_cpu, p_l3);
+	printf("%s + %s/%s\n", sysinfo.board_string,
+	       mem_s, bootmode[get_gpmc0_type()]);
+
+}
+
+/********************************************************
+ *  get_base(); get upper addr of current execution
+ *******************************************************/
+u32 get_base(void)
+{
+	u32 val;
+
+	__asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
+	val &= 0xF0000000;
+	val >>= 28;
+	return val;
+}
+
+/********************************************************
+ *  is_running_in_flash() - tell if currently running in
+ *  FLASH.
+ *******************************************************/
+u32 is_running_in_flash(void)
+{
+	if (get_base() < 4)
+		return 1;	/* in FLASH */
+
+	return 0;		/* running in SRAM or SDRAM */
+}
+
+/********************************************************
+ *  is_running_in_sram() - tell if currently running in
+ *  SRAM.
+ *******************************************************/
+u32 is_running_in_sram(void)
+{
+	if (get_base() == 4)
+		return 1;	/* in SRAM */
+
+	return 0;		/* running in FLASH or SDRAM */
+}
+
+/********************************************************
+ *  is_running_in_sdram() - tell if currently running in
+ *  SDRAM.
+ *******************************************************/
+u32 is_running_in_sdram(void)
+{
+	if (get_base() > 4)
+		return 1;	/* in SDRAM */
+
+	return 0;		/* running in SRAM or FLASH */
+}
+
+/***************************************************************
+ *  get_boot_type() - Is this an XIP type device or a stream one
+ *  bits 4-0 specify type.  Bit 5 sys mem/perif
+ ***************************************************************/
+u32 get_boot_type(void)
+{
+	u32 v;
+
+	v = get_sysboot_value() & (BIT4 | BIT3 | BIT2 | BIT1 | BIT0);
+	return v;
+}
+
+/*************************************************************
+ *  get_device_type(): tell if GP/HS/EMU/TST
+ *************************************************************/
+u32 get_device_type(void)
+{
+	int mode;
+
+	mode = readl(CONTROL_STATUS) & (DEVICE_MASK);
+	return mode >>= 8;
+}


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