[U-Boot] PATCH add support for cheflux board
Giulio Benetti
giulio.benetti at micronovasrl.com
Wed Nov 12 13:02:50 CET 2008
Add support for cheflux board
diff -urpN -X cheflux-exclude u-boot.orig/board/micronova/cheflux/cheflux.c
u-boot/board/micronova/cheflux/cheflux.c
--- u-boot.orig/board/micronova/cheflux/cheflux.c 1970-01-01
01:00:00.000000000 +0100
+++ u-boot/board/micronova/cheflux/cheflux.c 2008-11-12 12:49:06.000000000
+0100
@@ -0,0 +1,328 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop at leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * Giulio Benetti <giulio.benetti at micronovasrl.com>
+ * Micronova srl <info at micronovasrl.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/sizes.h>
+#include <asm/arch/at91sam9263.h>
+#include <asm/arch/at91sam9263_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+#include <lcd.h>
+#include <atmel_lcdc.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <net.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* -------------------------------------------------------------------------
*/
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+static void cheflux_serial_hw_init(void)
+{
+#ifdef CONFIG_USART0
+ at91_set_A_periph(AT91_PIN_PA26, 1); /* TXD0 */
+ at91_set_A_periph(AT91_PIN_PA27, 0); /* RXD0 */
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
+#endif
+
+#ifdef CONFIG_USART1
+ at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */
+ at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
+#endif
+
+#ifdef CONFIG_USART2
+ at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */
+ at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
+#endif
+
+#ifdef CONFIG_USART3 /* DBGU */
+ at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */
+ at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
+#endif
+}
+
+#ifdef CONFIG_CMD_NAND
+static void cheflux_nand_hw_init(void)
+{
+ unsigned long csa;
+
+ /* Enable CS3 */
+ csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
+ at91_sys_write(AT91_MATRIX_EBI0CSA,
+ csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ at91_sys_write(AT91_SMC_SETUP(3),
+ AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
+ AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
+ at91_sys_write(AT91_SMC_PULSE(3),
+ AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
+ AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
+ at91_sys_write(AT91_SMC_CYCLE(3),
+ AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
+ at91_sys_write(AT91_SMC_MODE(3),
+ AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+ AT91_SMC_EXNWMODE_DISABLE |
+#ifdef CFG_NAND_DBW_16
+ AT91_SMC_DBW_16 |
+#else /* CFG_NAND_DBW_8 */
+ AT91_SMC_DBW_8 |
+#endif
+ AT91_SMC_TDF_(2));
+
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOA |
+ 1 << AT91SAM9263_ID_PIOCDE);
+
+ /* Configure RDY/BSY */
+ at91_set_gpio_input(AT91_PIN_PA22, 1);
+
+ /* Enable NandFlash */
+ at91_set_gpio_output(AT91_PIN_PD15, 1);
+}
+#endif
+
+#ifdef CONFIG_HAS_DATAFLASH
+static void cheflux_spi_hw_init(void)
+{
+ at91_set_B_periph(AT91_PIN_PA5, 0); /* SPI0_NPCS0 */
+
+ at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
+ at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
+ at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
+
+ /* Enable clock */
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_SPI0);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void cheflux_macb_hw_init(void)
+{
+ /* Enable clock */
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
+
+ writel(pin_to_mask(AT91_PIN_PC22) |
+ pin_to_mask(AT91_PIN_PC23) |
+ pin_to_mask(AT91_PIN_PC25) |
+ pin_to_mask(AT91_PIN_PC27),
+ pin_to_controller(AT91_PIN_PC0) + PIO_PUDR);
+ writel(pin_to_mask(AT91_PIN_PE25) |
+ pin_to_mask(AT91_PIN_PE26) |
+ pin_to_mask(AT91_PIN_PE27),
+ pin_to_controller(AT91_PIN_PE0) + PIO_PUDR);
+
+ at91_set_gpio_output(AT91_PIN_PE22,1);
+ at91_set_gpio_output(AT91_PIN_PC21,0);
+ at91_set_gpio_output(AT91_PIN_PC26,1);
+
+ /* Need to reset PHY -> 500ms reset */
+ at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
+ (AT91_RSTC_ERSTL & (0x0D << 8)) |
+ AT91_RSTC_URSTEN);
+
+ at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
+
+ /* Wait for end hardware reset */
+ while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
+
+ /* Restore NRST value */
+ at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
+ (AT91_RSTC_ERSTL & (0x0E << 8)) |
+ AT91_RSTC_URSTEN);
+
+ /* Re-enable pull-up */
+ writel(pin_to_mask(AT91_PIN_PC22) |
+ pin_to_mask(AT91_PIN_PC23) |
+ pin_to_mask(AT91_PIN_PC25) |
+ pin_to_mask(AT91_PIN_PC27),
+ pin_to_controller(AT91_PIN_PC0) + PIO_PUER);
+ writel(pin_to_mask(AT91_PIN_PE25) |
+ pin_to_mask(AT91_PIN_PE26) |
+ pin_to_mask(AT91_PIN_PE27),
+ pin_to_controller(AT91_PIN_PE0) + PIO_PUER);
+
+ at91_set_A_periph(AT91_PIN_PE21, 0); /* ETXCK_EREFCK */
+ at91_set_B_periph(AT91_PIN_PC25, 0); /* ERXDV */
+ at91_set_A_periph(AT91_PIN_PE25, 0); /* ERX0 */
+ at91_set_A_periph(AT91_PIN_PE26, 0); /* ERX1 */
+ at91_set_A_periph(AT91_PIN_PE27, 0); /* ERXER */
+ at91_set_A_periph(AT91_PIN_PE28, 0); /* ETXEN */
+ at91_set_A_periph(AT91_PIN_PE23, 0); /* ETX0 */
+ at91_set_A_periph(AT91_PIN_PE24, 0); /* ETX1 */
+ at91_set_A_periph(AT91_PIN_PE30, 0); /* EMDIO */
+ at91_set_A_periph(AT91_PIN_PE29, 0); /* EMDC */
+
+#ifndef CONFIG_RMII
+ at91_set_A_periph(AT91_PIN_PE22, 0); /* ECRS */
+ at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */
+ at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */
+ at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */
+ at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */
+ at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */
+ at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */
+ at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */
+#endif
+
+}
+#endif
+
+#ifdef CONFIG_USB_OHCI_NEW
+static void cheflux_uhp_hw_init(void)
+{
+ /* Enable VBus on UHP ports */
+ at91_set_gpio_output(AT91_PIN_PA13, 0);
+ at91_set_gpio_output(AT91_PIN_PA18, 0);
+}
+#endif
+
+#ifdef CONFIG_LCD
+vidinfo_t panel_info = {
+ vl_col: 640,
+ vl_row: 480,
+ vl_clk: 25000000,
+ vl_sync: ATMEL_LCDC_INVLINE_INVERTED |
+ ATMEL_LCDC_INVFRAME_INVERTED,
+ vl_bpix: 3,
+ vl_tft: 1,
+ vl_hsync_len: 4,
+ vl_left_margin: 16,
+ vl_right_margin:8,
+ vl_vsync_len: 1,
+ vl_upper_margin:8,
+ vl_lower_margin:5,
+ mmio: AT91SAM9263_LCDC_BASE,
+};
+
+void lcd_enable(void)
+{
+ at91_set_gpio_value(AT91_PIN_PA30, 1); /* power up */
+}
+
+void lcd_disable(void)
+{
+ at91_set_gpio_value(AT91_PIN_PA30, 0); /* power down */
+}
+
+static void cheflux_lcd_hw_init(void)
+{
+ at91_set_A_periph(AT91_PIN_PC0, 0); /* LCDVSYNC */
+ at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
+ at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
+ at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */
+ at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */
+ at91_set_B_periph(AT91_PIN_PC4, 0); /* R1 */
+ at91_set_B_periph(AT91_PIN_PC5, 0); /* R2 */
+ at91_set_B_periph(AT91_PIN_PC6, 0); /* R3 */
+ at91_set_B_periph(AT91_PIN_PC7, 0); /* R4 */
+ at91_set_B_periph(AT91_PIN_PC8, 0); /* R5 */
+ at91_set_B_periph(AT91_PIN_PC9, 0); /* G0 */
+ at91_set_B_periph(AT91_PIN_PC10, 0); /* G1 */
+ at91_set_B_periph(AT91_PIN_PC11, 0); /* G2 */
+ at91_set_B_periph(AT91_PIN_PC12, 0); /* G3 */
+ at91_set_B_periph(AT91_PIN_PC13, 0); /* G4 */
+ at91_set_B_periph(AT91_PIN_PC14, 0); /* G5 */
+ at91_set_B_periph(AT91_PIN_PC15, 0); /* B1 */
+ at91_set_B_periph(AT91_PIN_PC16, 0); /* B2 */
+ at91_set_B_periph(AT91_PIN_PC17, 0); /* B3 */
+ at91_set_B_periph(AT91_PIN_PC18, 0); /* B4 */
+ at91_set_B_periph(AT91_PIN_PC19, 0); /* B5 */
+
+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_LCDC);
+
+ gd->fb_base = PHYS_SDRAM + 0x3FB5000; /* mapped into sdram @ 0x20000000 +
(64 MByte - (640x480) 8bpp) */
+}
+#endif
+
+#ifdef CONFIG_PCK
+static void cheflux_set_pck(void)
+{
+ at91_sys_write(AT91_PMC_PCKR(1), 7); /* Put clock @ 48 Mhz on PCK1 => PLLB/2
*/
+ at91_sys_write(AT91_PMC_SCER, AT91_PMC_PCK | AT91_PMC_PCK1); /* Enable PCK1
*/
+ at91_set_B_periph(AT91_PIN_PB10, 0); /* Set B on PB10 for PCK1 */
+}
+#endif
+
+int board_init(void)
+{
+ /* Enable Ctrlc */
+ console_init_f();
+
+ /* arch number of CHEFLUX-Board */
+ gd->bd->bi_arch_number = MACH_TYPE_CHEFLUX;
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ cheflux_serial_hw_init();
+#ifdef CONFIG_PCK
+ cheflux_set_pck();
+#endif
+#ifdef CONFIG_CMD_NAND
+ cheflux_nand_hw_init();
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+ cheflux_spi_hw_init();
+#endif
+#ifdef CONFIG_MACB
+ cheflux_macb_hw_init();
+#endif
+#ifdef CONFIG_USB_OHCI_NEW
+ cheflux_uhp_hw_init();
+#endif
+#ifdef CONFIG_LCD
+ cheflux_lcd_hw_init();
+#endif
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+#ifdef CONFIG_MACB
+ /*
+ * Initialize ethernet HW addr prior to starting Linux,
+ * needed for nfsroot
+ */
+ eth_init(gd->bd);
+#endif
+}
+#endif
diff -urpN -X cheflux-exclude u-boot.orig/board/micronova/cheflux/config.mk
u-boot/board/micronova/cheflux/config.mk
--- u-boot.orig/board/micronova/cheflux/config.mk 1970-01-01
01:00:00.000000000 +0100
+++ u-boot/board/micronova/cheflux/config.mk 2008-08-12 16:08:38.000000000
+0200
@@ -0,0 +1 @@
+TEXT_BASE = 0x23f00000
diff -urpN -X cheflux-exclude u-boot.orig/board/micronova/cheflux/Makefile
u-boot/board/micronova/cheflux/Makefile
--- u-boot.orig/board/micronova/cheflux/Makefile 1970-01-01 01:00:00.000000000
+0100
+++ u-boot/board/micronova/cheflux/Makefile 2008-11-10 09:51:06.000000000
+0100
@@ -0,0 +1,59 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian.pop at leadtechdesign.com>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# Giulio Benetti <giulio.benetti at micronovasrl.com>
+# Micronova srl <info at micronovasrl.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y += cheflux.o
+COBJS-y += partition.o
+COBJS-$(CONFIG_CMD_NAND) += nand.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff -urpN -X cheflux-exclude u-boot.orig/board/micronova/cheflux/nand.c
u-boot/board/micronova/cheflux/nand.c
--- u-boot.orig/board/micronova/cheflux/nand.c 1970-01-01 01:00:00.000000000
+0100
+++ u-boot/board/micronova/cheflux/nand.c 2008-08-12 16:08:38.000000000 +0200
@@ -0,0 +1,79 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop at leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9263.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/at91_pio.h>
+
+#include <nand.h>
+
+/*
+ * hardware specific access to control-lines
+ */
+#define MASK_ALE (1 << 21) /* our ALE is AD21 */
+#define MASK_CLE (1 << 22) /* our CLE is AD22 */
+
+static void at91sam9263ek_nand_hwcontrol(struct mtd_info *mtd, int cmd)
+{
+ struct nand_chip *this = mtd->priv;
+ ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+
+ IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
+ switch (cmd) {
+ case NAND_CTL_SETCLE:
+ IO_ADDR_W |= MASK_CLE;
+ break;
+ case NAND_CTL_SETALE:
+ IO_ADDR_W |= MASK_ALE;
+ break;
+ case NAND_CTL_CLRNCE:
+ at91_set_gpio_value(AT91_PIN_PD15, 1);
+ break;
+ case NAND_CTL_SETNCE:
+ at91_set_gpio_value(AT91_PIN_PD15, 0);
+ break;
+ }
+ this->IO_ADDR_W = (void *) IO_ADDR_W;
+}
+
+static int at91sam9263ek_nand_ready(struct mtd_info *mtd)
+{
+ return at91_get_gpio_value(AT91_PIN_PA22);
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+ nand->eccmode = NAND_ECC_SOFT;
+#ifdef CFG_NAND_DBW_16
+ nand->options = NAND_BUSWIDTH_16;
+#endif
+ nand->hwcontrol = at91sam9263ek_nand_hwcontrol;
+ nand->dev_ready = at91sam9263ek_nand_ready;
+ nand->chip_delay = 20;
+
+ return 0;
+}
diff -urpN -X cheflux-exclude u-boot.orig/board/micronova/cheflux/partition.c
u-boot/board/micronova/cheflux/partition.c
--- u-boot.orig/board/micronova/cheflux/partition.c 1970-01-01
01:00:00.000000000 +0100
+++ u-boot/board/micronova/cheflux/partition.c 2008-11-12 12:49:41.000000000
+0100
@@ -0,0 +1,39 @@
+/*
+ * (C) Copyright 2008
+ * Ulf Samuelsson <ulf at atmel.com>
+ * Giulio Benetti <giulio.benetti at micronovasrl.com>
+ * Micronova srl <info at micronovasrl.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = {
+ {CFG_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
+};
+
+/*define the area offsets*/
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+ {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
+ {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+ {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
+};
diff -urpN -X cheflux-exclude u-boot.orig/CREDITS u-boot/CREDITS
--- u-boot.orig/CREDITS 2008-08-12 16:08:38.000000000 +0200
+++ u-boot/CREDITS 2008-11-12 12:54:39.000000000 +0100
@@ -399,6 +399,10 @@ N: Stelian Pop
E: stelian.pop at leadtechdesign.com
D: Atmel AT91CAP9ADK support
+N: Giulio Benetti
+E: giulio.benetti at micronovasrl.com
+D: Micronova boards support
+
N: Stefan Roese
E: sr at denx.de
D: AMCC PPC4xx Support
diff -urpN -X cheflux-exclude u-boot.orig/include/configs/cheflux.h
u-boot/include/configs/cheflux.h
--- u-boot.orig/include/configs/cheflux.h 1970-01-01 01:00:00.000000000 +0100
+++ u-boot/include/configs/cheflux.h 2008-11-12 12:50:34.000000000 +0100
@@ -0,0 +1,201 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop at leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * Giulio Benetti <giulio.benetti at micronovasrl.com>
+ * Micronova srl <info at micronovasrl.com>
+ *
+ * Configuation settings for the CHEFLUX board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* ARM asynchronous clock */
+#define AT91_CPU_NAME "AT91SAM9263"
+#define AT91_MAIN_CLOCK 240000000 /* from 20.000 MHz crystal */
+#define AT91_MASTER_CLOCK 120000000 /* peripheral = main / 2 */
+#define CFG_HZ 1000000 /* 1us resolution */
+
+#define AT91_SLOW_CLOCK 32768 /* slow clock */
+
+#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
+#define CONFIG_AT91SAM9263 1 /* It's an Atmel AT91SAM9263 SoC*/
+#define CONFIG_AT91SAM9263EK 1 /* on an AT91SAM9263EK Board */
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_ATMEL_USART 1
+#undef CONFIG_USART0
+#undef CONFIG_USART1
+#undef CONFIG_USART2
+#define CONFIG_USART3 1 /* USART 3 is DBGU */
+
+/* LCD */
+#define CONFIG_LCD 1
+#define LCD_BPP LCD_COLOR8
+#define CONFIG_LCD_LOGO 1
+#undef LCD_TEST_PATTERN
+#define CONFIG_LCD_INFO 1
+#define CONFIG_LCD_INFO_BELOW_LOGO 1
+#define CFG_WHITE_ON_BLACK 1
+#define CONFIG_ATMEL_LCD 1
+#define CONFIG_ATMEL_LCD_BGR555 1
+#define CFG_CONSOLE_IS_IN_ENV 1
+
+#define CONFIG_BOOTDELAY 3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE 1
+#define CONFIG_BOOTP_BOOTPATH 1
+#define CONFIG_BOOTP_GATEWAY 1
+#define CONFIG_BOOTP_HOSTNAME 1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_CMD_PING 1
+#define CONFIG_CMD_DHCP 1
+#define CONFIG_CMD_NAND 1
+#define CONFIG_CMD_USB 1
+
+/* PCK */
+#define CONFIG_PCK
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM 0x20000000
+#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
+
+/* DataFlash */
+#define CONFIG_HAS_DATAFLASH 1
+#define CFG_SPI_WRITE_TOUT (5*CFG_HZ)
+#define CFG_MAX_DATAFLASH_BANKS 1
+#define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
+#define AT91_SPI_CLK 15000000
+#define DATAFLASH_TCSS (0x1a << 16)
+#define DATAFLASH_TCHS (0x1 << 24)
+
+/* NOR flash, if populated */
+#if 1
+#define CFG_NO_FLASH 1
+#else
+#define CFG_FLASH_CFI 1
+#define CFG_FLASH_CFI_DRIVER 1
+#define PHYS_FLASH_1 0x10000000
+#define CFG_FLASH_BASE PHYS_FLASH_1
+#define CFG_MAX_FLASH_SECT 256
+#define CFG_MAX_FLASH_BANKS 1
+#endif
+
+/* NAND flash */
+#define NAND_MAX_CHIPS 1
+#define CFG_MAX_NAND_DEVICE 1
+#define CFG_NAND_BASE 0x40000000
+#define CFG_NAND_DBW_8 1
+
+/* Ethernet */
+#define CONFIG_MACB 1
+#define CONFIG_RMII 1
+#define CONFIG_NET_MULTI 1
+#define CONFIG_NET_RETRY_COUNT 20
+#define CONFIG_RESET_PHY_R 1
+
+/* USB */
+#define CONFIG_USB_OHCI_NEW 1
+#define LITTLEENDIAN 1
+#define CONFIG_DOS_PARTITION 1
+#define CFG_USB_OHCI_CPU_INIT 1
+#define CFG_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
+#define CFG_USB_OHCI_SLOT_NAME "at91sam9263"
+#define CFG_USB_OHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_STORAGE 1
+
+#define CFG_LOAD_ADDR 0x22000000 /* load address */
+
+#define CFG_MEMTEST_START PHYS_SDRAM
+#define CFG_MEMTEST_END 0x23e00000
+
+#define CFG_USE_DATAFLASH 1
+#undef CFG_USE_NANDFLASH
+
+#ifdef CFG_USE_DATAFLASH
+
+/* bootstrap + u-boot + env + linux in dataflash on CS0 */
+#define CFG_ENV_IS_IN_DATAFLASH 1
+#define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
+#define CFG_ENV_OFFSET 0x4200
+#define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET)
+#define CFG_ENV_SIZE 0x4200
+
+#else /* CFG_USE_NANDFLASH */
+
+/* bootstrap + u-boot + env + linux in nandflash */
+#define CFG_ENV_IS_IN_NAND 1
+#define CFG_ENV_OFFSET 0x60000
+#define CFG_ENV_OFFSET_REDUND 0x80000
+#define CFG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
+
+#endif
+
+#define CONFIG_BAUDRATE 115200
+#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
+
+#define CFG_PROMPT "U-Boot> "
+#define CFG_CBSIZE 256
+#define CFG_MAXARGS 16
+#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define CFG_LONGHELP 1
+#define CONFIG_CMDLINE_EDITING 1
+
+#define ROUND(A, B) (((A) + (B)) & ~((B) - 1))
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN ROUND(3 * CFG_ENV_SIZE + 128*1024, 0x1000)
+#define CFG_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
+
+#define CONFIG_STACKSIZE (32*1024) /* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif
diff -urpN -X cheflux-exclude u-boot.orig/MAINTAINERS u-boot/MAINTAINERS
--- u-boot.orig/MAINTAINERS 2008-08-12 16:08:38.000000000 +0200
+++ u-boot/MAINTAINERS 2008-11-12 12:53:51.000000000 +0100
@@ -586,6 +586,10 @@ Alex Z�pke <azu at sysgo.de>
lart SA1100
dnp1110 SA1110
+Giulio Benetti <giulio.benetti at micronovasrl.com>
+
+ cheflux ARM926EJS (AT91SAM9263 SoC)
+
-------------------------------------------------------------------------
Unknown / orphaned boards:
diff -urpN -X cheflux-exclude u-boot.orig/Makefile u-boot/Makefile
--- u-boot.orig/Makefile 2008-08-12 16:08:38.000000000 +0200
+++ u-boot/Makefile 2008-11-10 09:54:27.000000000 +0100
@@ -2353,15 +2353,6 @@ shannon_config : unconfig
at91rm9200dk_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t at91rm9200dk atmel at91rm9200
-at91sam9261ek_config : unconfig
- @$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9261ek atmel at91sam9
-
-at91sam9263ek_config : unconfig
- @$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9263ek atmel at91sam9
-
-at91sam9rlek_config : unconfig
- @$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9rlek atmel at91sam9
-
cmc_pu2_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t cmc_pu2 NULL at91rm9200
@@ -2387,6 +2378,18 @@ at91cap9adk_config : unconfig
at91sam9260ek_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9260ek atmel at91sam9
+at91sam9261ek_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9261ek atmel at91sam9
+
+at91sam9263ek_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9263ek atmel at91sam9
+
+at91sam9rlek_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm926ejs at91sam9rlek atmel at91sam9
+
+cheflux_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm926ejs cheflux micronova at91sam9
+
########################################################################
## ARM Integrator boards - see doc/README-integrator for more info.
integratorap_config \
Signed-off-by: Giulio Benetti <giulio.benetti at micronovasrl.com>
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