[U-Boot] [PATCH-OMAP3] OMAP3: Clean up EVM board file
dirk.behme at googlemail.com
dirk.behme at googlemail.com
Sat Nov 15 21:29:06 CET 2008
- Use readx/writex instead of direct pointer access
- Replace hardcoded values by macros
- Minor space to tab conversion
Notes:
- Instead of read/modify/write GPIO_DATAOUT register use SET/CLEARDATAOUT
register for GPIO64
- GPIO 1-6 CM_FCLKEN_PER and CM_ICLKEN_PER are already configured in
per_clocks_enable(), remove it here
- Remove pin mux. Is done in set_muxconf_regs.
No functional change.
Signed-off-by: Dirk Behme <dirk.behme at gmail.com>
---
board/omap3/evm/evm.c | 143 +++++++++----------------------------
board/omap3/evm/evm.h | 64 ++++++++--------
include/asm-arm/arch-omap3/cpu.h | 2
include/asm-arm/arch-omap3/mem.h | 8 ++
include/asm-arm/arch-omap3/omap3.h | 1
5 files changed, 78 insertions(+), 140 deletions(-)
Index: u-boot-arm/board/omap3/evm/evm.c
===================================================================
--- u-boot-arm.orig/board/omap3/evm/evm.c
+++ u-boot-arm/board/omap3/evm/evm.c
@@ -3,12 +3,11 @@
* Texas Instruments, <www.ti.com>
*
* Author :
- * Manikandan Pillai <mani.pillai at ti.com>
+ * Manikandan Pillai <mani.pillai at ti.com>
*
* Derived from Beagle Board and 3430 SDP code by
- * Richard Woodruff <r-woodruff2 at ti.com>
- * Syed Mohammed Khasim <khasim at ti.com>
- *
+ * Richard Woodruff <r-woodruff2 at ti.com>
+ * Syed Mohammed Khasim <khasim at ti.com>
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -30,6 +29,7 @@
*/
#include <common.h>
#include <asm/io.h>
+#include <asm/arch/mem.h>
#include <asm/arch/mux.h>
#include <asm/arch/sys_proto.h>
#include <i2c.h>
@@ -74,8 +74,8 @@ int misc_init_r(void)
/******************************************************************************
* Routine: set_muxconf_regs
* Description: Setting up the configuration Mux registers specific to the
- * hardware. Many pins need to be moved from protect to primary
- * mode.
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
*****************************************************************************/
void set_muxconf_regs(void)
{
@@ -85,115 +85,42 @@ void set_muxconf_regs(void)
/******************************************************************************
* Routine: setup_net_chip
* Description: Setting up the configuration GPMC registers specific to the
- * Ethernet hardware. Pin Muxing for the SMC9118 is initialized
- * here.
+ * Ethernet hardware.
*****************************************************************************/
-static int setup_net_chip(void)
+static void setup_net_chip(void)
{
- int i = 0;
+ unsigned int *gpio3_base = (unsigned int *)OMAP34XX_GPIO3_BASE;
+ unsigned int *gpmc_cs6_base = (unsigned int *)GPMC_CONFIG_CS6_BASE;
+ unsigned short *ctrl_base = (unsigned short *)OMAP34XX_CTRL_BASE;
/* Configure GPMC registers */
- (*(volatile int *)(OMAP34XX_GPMC_BASE + 0x0150)) = 0x00001000;
- (*(volatile int *)(OMAP34XX_GPMC_BASE + 0x0154)) = 0x001e1e01;
- (*(volatile int *)(OMAP34XX_GPMC_BASE + 0x0158)) = 0x00080300;
- (*(volatile int *)(OMAP34XX_GPMC_BASE + 0x015C)) = 0x1c091c09;
- (*(volatile int *)(OMAP34XX_GPMC_BASE + 0x0160)) = 0x04181f1f;
- (*(volatile int *)(OMAP34XX_GPMC_BASE + 0x0164)) = 0x00000FCF;
- (*(volatile int *)(OMAP34XX_GPMC_BASE + 0x0168)) = 0x00000f6c;
-
- /*
- * Configure PIN MUX registers
- * Enable GPMC Pin Mux Registers
- * Enable GPMC_CLK Pin in CONTROL_PADCONF_gpmc_ncs7 register
- */
- (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xBC)) |= 0x00180000;
- /* Enable CS5 Pin in CONTROL_PADCONF_gpmc_ncs5 register */
- (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xB8)) |= 0x00000018;
- (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xB8)) &= 0xFFFFFFF8;
- /* Enable offmode for nwe in CONTROL_PADCONF_GPMC_NWE register */
- (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xC4)) |= 0x00000F00;
- /* En off mode for noe and ale in CONTROL_PADCONF_GPMC_NADV_ALE reg */
- (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xC0)) |= 0x0E000E00;
- /* Enable gpmc_nbe0_cle in CONTROL_PADCONF_GPMC_NWE register */
- (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xC4)) |= 0x00180000;
-
- /*
- * Enable gpmc_nbe1 in CONTROL_PADCONF_GPMC_NBE1 register and
- * configuring the mux mode to 0
- */
- (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xC8)) |= 0x00000018;
- (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xC8)) &= 0xFFFFFFF8;
- /* Enable d15 in CONTROL_PADCONF_GPMC_D15 register */
- (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xAC)) |= 0x00000018;
- /* Enable d14 - d13 in CONTROL_PADCONF_GPMC_D13 register */
- (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xA8)) |= 0x00180018;
- /* Enable d12 - d11 in CONTROL_PADCONF_GPMC_D11 register */
- (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xA4)) |= 0x00180018;
- /* Enable d10 - d9 in CONTROL_PADCONF_GPMC_D9 register */
- (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xA0)) |= 0x00180018;
- /* Enable d8 - d7 in CONTROL_PADCONF_GPMC_D7 register */
- (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x9C)) |= 0x00180018;
- /* Enable d6 - d5 in CONTROL_PADCONF_GPMC_D5 register */
- (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x98)) |= 0x00180018;
- /* Enable d4 - d3 in CONTROL_PADCONF_GPMC_D3 register */
- (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x94)) |= 0x00180018;
- /* Enable d2 - d1 in CONTROL_PADCONF_GPMC_D1 register */
- (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x90)) |= 0x00180018;
- /* Enable d0 and a10 in CONTROL_PADCONF_GPMC_a10 register */
- (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x8C)) |= 0x00180018;
- (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x8C)) &= 0xFFFFFFF8;
- /* Enable a9 - a8 in CONTROL_PADCONF_GPMC_a8 register */
- (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x88)) |= 0x00180018;
- (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x88)) &= 0xFFF8FFF8;
- /* Enable a7 - a6 in CONTROL_PADCONF_GPMC_a6 register */
- (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x84)) |= 0x00180018;
- (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x84)) &= 0xFFF8FFF8;
- /* Enable a5 - a4 in CONTROL_PADCONF_GPMC_a4 register */
- (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x80)) |= 0x00180018;
- (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x80)) &= 0xFFF8FFF8;
- /* Enable a3 - a2 in CONTROL_PADCONF_GPMC_a2 register */
- (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x7C)) |= 0x00180018;
- (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x7C)) &= 0xFFF8FFF8;
- /* Enable a1 - a0 in CONTROL_PADCONF_GPMC_a0 register */
- (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x78)) |= 0x00000018;
- (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x78)) &= 0xFFFFFFF8;
-
-#if defined(CPU_3430_ES1) || defined(CPU_3430_ES2)
- /*
- * GPIO 64 configuration in CONTROL_PADCONF_GPMC_WAIT2
- * register mux mode is 4.
- */
- (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xD0)) |= 0x00000018;
- (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xD0)) &= 0xFFFFFFF8;
- (*(volatile int *)(OMAP34XX_CTRL_BASE + 0xD0)) |= 0x00000004;
-
- /*
- * Configure GPIO 176 in CONTROL_PADCONF_MCSPI1_CS1
- * register for ethernet ISR mux mode is 4
- */
- (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x1D0)) |= 0x00180000;
- (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x1D0)) &= 0xFFF8FFFF;
- (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x1D0)) |= 0x00040000;
-
- /*
- * Enable Clock for GPIO 1-6 module in CM_FCLKEN_PER
- * and CM_ICLKEN_PER registers
- */
- (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x5000)) |= 0x0003E800;
- (*(volatile int *)(OMAP34XX_CTRL_BASE + 0x5010)) |= 0x0003E800;
+ writel(NET_GPMC_CONFIG1, gpmc_cs6_base + OFFS(GPMC_CONFIG1));
+ writel(NET_GPMC_CONFIG2, gpmc_cs6_base + OFFS(GPMC_CONFIG2));
+ writel(NET_GPMC_CONFIG3, gpmc_cs6_base + OFFS(GPMC_CONFIG3));
+ writel(NET_GPMC_CONFIG4, gpmc_cs6_base + OFFS(GPMC_CONFIG4));
+ writel(NET_GPMC_CONFIG5, gpmc_cs6_base + OFFS(GPMC_CONFIG5));
+ writel(NET_GPMC_CONFIG6, gpmc_cs6_base + OFFS(GPMC_CONFIG6));
+ writel(NET_GPMC_CONFIG7, gpmc_cs6_base + OFFS(GPMC_CONFIG7));
+
+ /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
+ writew(readw(ctrl_base + (CONTROL_PADCONF_GPMC_NWE >> 1)) | 0x0E00,
+ ctrl_base + (CONTROL_PADCONF_GPMC_NWE >> 1));
+ /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(ctrl_base + (CONTROL_PADCONF_GPMC_NOE >> 1)) | 0x0E00,
+ ctrl_base + (CONTROL_PADCONF_GPMC_NOE >> 1));
+ /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(ctrl_base + (CONTROL_PADCONF_GPMC_NADV_ALE >> 1)) | 0x0E00,
+ ctrl_base + (CONTROL_PADCONF_GPMC_NADV_ALE >> 1));
/* Make GPIO 64 as output pin */
- (*(volatile int *)(OMAP34XX_GPIO3_BASE + 0x34)) &= ~(0x00000001);
+ writel(readl(gpio3_base + OFFS(GPIO_OE)) & ~(GPIO0),
+ gpio3_base + OFFS(GPIO_OE));
/* Now send a pulse on the GPIO pin */
- (*(volatile int *)(OMAP34XX_GPIO3_BASE + 0x3C)) |= 0x00000001;
- for (i = 0; i < 99 ; i++);
- (*(volatile int *)(OMAP34XX_GPIO3_BASE + 0x3C)) &= ~(0x00000001);
- for (i = 0; i < 99 ; i++);
- (*(volatile int *)(OMAP34XX_GPIO3_BASE + 0x3C)) |= 0x00000001;
-#else
- printf("Unknown revision... \n\n");
-#endif
- return 0;
+ writel(GPIO0, gpio3_base + OFFS(GPIO_SETDATAOUT));
+ udelay(1);
+ writel(GPIO0, gpio3_base + OFFS(GPIO_CLEARDATAOUT));
+ udelay(1);
+ writel(GPIO0, gpio3_base + OFFS(GPIO_SETDATAOUT));
}
Index: u-boot-arm/board/omap3/evm/evm.h
===================================================================
--- u-boot-arm.orig/board/omap3/evm/evm.h
+++ u-boot-arm/board/omap3/evm/evm.h
@@ -36,7 +36,7 @@ const omap3_sysinfo sysinfo = {
#endif
};
-static int setup_net_chip(void);
+static void setup_net_chip(void);
/*
* IEN - Input Enable
@@ -88,46 +88,46 @@ static int setup_net_chip(void);
MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
/*GPMC*/\
- MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
- MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
- MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
- MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
- MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
- MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
- MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
- MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
- MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
- MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
- MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
- MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
- MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
- MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
- MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
- MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
- MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
- MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
- MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
- MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
- MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
- MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
- MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
- MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
- MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
- MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) /*GPMC_A8*/\
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) /*GPMC_A9*/\
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) /*GPMC_A10*/\
+ MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) /*GPMC_D0*/\
+ MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) /*GPMC_D1*/\
+ MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) /*GPMC_D2*/\
+ MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) /*GPMC_D3*/\
+ MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) /*GPMC_D4*/\
+ MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) /*GPMC_D5*/\
+ MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) /*GPMC_D6*/\
+ MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) /*GPMC_D7*/\
+ MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) /*GPMC_D8*/\
+ MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) /*GPMC_D9*/\
+ MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) /*GPMC_D10*/\
+ MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) /*GPMC_D11*/\
+ MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) /*GPMC_D12*/\
+ MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) /*GPMC_D13*/\
+ MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/\
+ MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/\
MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)) /*GPMC_nCS4*/\
- MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M0)) /*GPMC_nCS5*/\
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\
MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)) /*GPMC_nCS6*/\
MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)) /*GPMC_nCS7*/\
- MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) /*GPMC_CLK*/\
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
- MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
- MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nBE1*/\
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) /*GPMC_nBE0_CLE*/\
+ MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M0)) /*GPMC_nBE1*/\
MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
@@ -278,7 +278,7 @@ static int setup_net_chip(void);
MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\
MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\
/* TS_PEN_IRQ */\
- MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | DIS | M4)) /*GPIO_176*/\
+ MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176*/\
/* - LAN_INTR*/\
MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)) /*McSPI1_CS3*/\
MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) /*McSPI2_CLK*/\
Index: u-boot-arm/include/asm-arm/arch-omap3/cpu.h
===================================================================
--- u-boot-arm.orig/include/asm-arm/arch-omap3/cpu.h
+++ u-boot-arm/include/asm-arm/arch-omap3/cpu.h
@@ -56,9 +56,11 @@
#define GPMC_CONFIG 0x50
#define GPMC_STATUS 0x54
#define GPMC_CONFIG_CS0 0x60
+#define GPMC_CONFIG_CS6 0x150
#define GPMC_CONFIG_REG (GPMC_BASE + GPMC_CONFIG)
#define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0)
+#define GPMC_CONFIG_CS6_BASE (GPMC_BASE + GPMC_CONFIG_CS6)
#define GPMC_CONFIG_WP 0x10
#define GPMC_CONFIG_WIDTH 0x30
Index: u-boot-arm/include/asm-arm/arch-omap3/mem.h
===================================================================
--- u-boot-arm.orig/include/asm-arm/arch-omap3/mem.h
+++ u-boot-arm/include/asm-arm/arch-omap3/mem.h
@@ -197,6 +197,14 @@ typedef enum {
#define ONENAND_GPMC_CONFIG5 0x010F1010
#define ONENAND_GPMC_CONFIG6 0x1F060000
+#define NET_GPMC_CONFIG1 0x00001000
+#define NET_GPMC_CONFIG2 0x001e1e01
+#define NET_GPMC_CONFIG3 0x00080300
+#define NET_GPMC_CONFIG4 0x1c091c09
+#define NET_GPMC_CONFIG5 0x04181f1f
+#define NET_GPMC_CONFIG6 0x00000FCF
+#define NET_GPMC_CONFIG7 0x00000f6c
+
/* max number of GPMC Chip Selects */
#define GPMC_MAX_CS 8
/* max number of GPMC regs */
Index: u-boot-arm/include/asm-arm/arch-omap3/omap3.h
===================================================================
--- u-boot-arm.orig/include/asm-arm/arch-omap3/omap3.h
+++ u-boot-arm/include/asm-arm/arch-omap3/omap3.h
@@ -86,6 +86,7 @@
#define OMAP34XX_GPIO6_BASE 0x49058000
#define GPIO_OE 0x34
+#define GPIO_CLEARDATAOUT 0x90
#define GPIO_SETDATAOUT 0x94
#define GPIO0 (0x1 << 0)
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