[U-Boot] [PATCH] MIPS: Add CONFIG_SKIP_LOWLEVEL_INIT and flush dcache upon relocation

[Stefan Roese]

On Sunday 16 November 2008, Shinya Kuribayashi wrote:
> > diff --git a/cpu/mips/start.S b/cpu/mips/start.S
> > index 6a22302..5b71b00 100644
> > --- a/cpu/mips/start.S
> > +++ b/cpu/mips/start.S
> > @@ -243,9 +243,11 @@ reset:
> >  	mtc0	zero, CP0_COUNT
> >  	mtc0	zero, CP0_COMPARE
> >
> > +#if !defined(CONFIG_SKIP_LOWLEVEL_INIT)
> >  	/* CONFIG0 register */
> >  	li	t0, CONF_CM_UNCACHED
> >  	mtc0	t0, CP0_CONFIG
> > +#endif /* !CONFIG_SKIP_LOWLEVEL_INIT */
> >
> >  	/* Initialize $gp.
> >  	 */
>
> It might be preferable to remove the /* CONFIG_SKIP_LOWLEVEL_INIT */
> comment for better readability, IMHO.

Hmmm. I usually prefer to add those comments to the #else and #endif since it 
makes the code better readable. Especially when the chunks of code in-between 
gets bigger. So I would prefer to keep this comment. OK?

> > @@ -323,6 +327,14 @@ relocate_code:
> >  	 * t1 = target address
> >  	 * t2 = source end address
> >  	 */
> > +
> > +	/*
> > +	 * Save destination address and size for later usage in flush_cache()
> > +	 */
> > +	move	t7, a1		/* save gd in t7		*/
> > +	move	a0, t1		/* a0 <-- destination addr	*/
> > +	sub	a1, t2, t0	/* a1 <-- size			*/
> > +
> >  	/* On the purple board we copy the code earlier in a special way
> >  	 * in order to solve flash problems
> >  	 */
> > @@ -338,6 +350,11 @@ relocate_code:
> >  	/* If caches were enabled, we would have to flush them here.
> >  	 */
> >
> > +	/* a0 & a1 are already set up for flush_cache(start, size) */
> > +	la	t9, flush_cache
> > +	jalr	t9
> > +	nop
> > +
> >  	/* Jump to where we've relocated ourselves.
> >  	 */
> >  	addi	t0, a2, in_ram - _start
> > @@ -387,7 +404,7 @@ in_ram:
> >  	bltl	t1, t2, 1b
> >  	sw	zero, 0(t1)	/* delay slot			*/
> >
> > -	move	a0, a1
> > +	move	a0, t7		/* a0 <-- gd			*/
> >  	la	t9, board_init_r
> >  	jr	t9
> >  	move	a1, a2		/* delay slot			*/
>
> - Could we separate this flush_cache patch from this patch?

OK, will do.

> - Please use save register, s[0-7], instead of t7, since t7 register
>   might be overwritten with another value in flush_cache().
>   Furthermore, in this case, a2 should be saved as well.

I'm still new to MIPS so thanks for your suggestions. I'll try to provide a 
fixed up patch today.

Thanks.

Best regards,
Stefan

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