[U-Boot] [RFC PATCH V2 2/2] Add Freescale ehci USB support

Michael Trimarchi trimarchi at gandalf.sssup.it
Thu Nov 27 13:35:55 CET 2008


Add Freescale ehci USB support

Signed-off-by: Michael Trimarchi <trimarchi at gandalf.sssup.it>

---
 drivers/usb/Makefile       |    2 +
 drivers/usb/usb_ehci_fsl.c |   99 ++++++++++++++++++++++++++++++++++++++++++++
 drivers/usb/usb_ehci_fsl.h |   82 ++++++++++++++++++++++++++++++++++++
 3 files changed, 183 insertions(+), 0 deletions(-)
 create mode 100644 drivers/usb/usb_ehci_fsl.c
 create mode 100644 drivers/usb/usb_ehci_fsl.h

diff --git a/drivers/usb/Makefile b/drivers/usb/Makefile
index 856f51a..6ba154b 100644
--- a/drivers/usb/Makefile
+++ b/drivers/usb/Makefile
@@ -28,11 +28,13 @@ LIB	:= $(obj)libusb.a
 # core
 COBJS-y += usbdcore.o
 COBJS-$(CONFIG_USB_OHCI_NEW) += usb_ohci.o
+COBJS-$(CONFIG_USB_EHCI) += usb_ehci_core.o
 
 # host
 COBJS-$(CONFIG_USB_ISP116X_HCD) += isp116x-hcd.o
 COBJS-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o
 COBJS-$(CONFIG_USB_SL811HS) += sl811_usb.o
+COBJS-$(CONFIG_USB_EHCI_FSL) += usb_ehci_fsl.o
 
 # device
 ifdef CONFIG_USB_DEVICE
diff --git a/drivers/usb/usb_ehci_fsl.c b/drivers/usb/usb_ehci_fsl.c
new file mode 100644
index 0000000..b88bda6
--- /dev/null
+++ b/drivers/usb/usb_ehci_fsl.c
@@ -0,0 +1,99 @@
+/*
+ * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB
+ *
+ * Author: Tor Krill tor at excito.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <usb.h>
+#include <mpc83xx.h>
+#include <asm/io.h>
+#include <asm/bitops.h>
+
+#include "usb_ehci.h"
+#include "usb_ehci_fsl.h"
+#include "usb_ehci_core.h"
+
+/*
+ * Create the appropriate control structures to manage
+ * a new EHCI host controller.
+ *
+ * Excerpts from linux ehci fsl driver.
+ */
+int ehci_hcd_init(void)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	uint32_t addr, temp;
+
+	addr = (uint32_t)&(im->usb[0]);
+	hccr = (struct ehci_hccr *)(addr + FSL_SKIP_PCI);
+	hcor = (struct ehci_hcor *)((uint32_t) hccr + hccr->cr_caplength);
+
+	/* Configure clock */
+	clrsetbits_be32(&(im->clk.sccr), MPC83XX_SCCR_USB_MASK,
+			MPC83XX_SCCR_USB_DRCM_11);
+
+	/* Confgure interface. */
+	temp = in_be32((void *)(addr + FSL_SOC_USB_CTRL));
+	out_be32((void *)(addr + FSL_SOC_USB_CTRL), temp
+		 | REFSEL_16MHZ | UTMI_PHY_EN);
+
+	/* Wait for clock to stabilize */
+	do {
+		temp = in_be32((void *)(addr + FSL_SOC_USB_CTRL));
+		udelay(1000);
+	} while (!(temp & PHY_CLK_VALID));
+
+	/* Set to Host mode */
+	temp = in_le32((void *)(addr + FSL_SOC_USB_USBMODE));
+	out_le32((void *)(addr + FSL_SOC_USB_USBMODE), temp | CM_HOST);
+
+	out_be32((void *)(addr + FSL_SOC_USB_SNOOP1), SNOOP_SIZE_2GB);
+	out_be32((void *)(addr + FSL_SOC_USB_SNOOP2),
+		 0x80000000 | SNOOP_SIZE_2GB);
+
+	/* Init phy */
+	/* TODO: handle different phys? */
+	out_le32(&(hcor->or_portsc[0]), PORT_PTS_UTMI);
+
+	/* Enable interface. */
+	temp = in_be32((void *)(addr + FSL_SOC_USB_CTRL));
+	out_be32((void *)(addr + FSL_SOC_USB_CTRL), temp | USB_EN);
+
+	out_be32((void *)(addr + FSL_SOC_USB_PRICTRL), 0x0000000c);
+	out_be32((void *)(addr + FSL_SOC_USB_AGECNTTHRSH), 0x00000040);
+	out_be32((void *)(addr + FSL_SOC_USB_SICTRL), 0x00000001);
+
+	/* Enable interface. */
+	temp = in_be32((void *)(addr + FSL_SOC_USB_CTRL));
+	out_be32((void *)(addr + FSL_SOC_USB_CTRL), temp | USB_EN);
+
+	temp = in_le32((void *)(addr + FSL_SOC_USB_USBMODE));
+
+	return 0;
+}
+
+/*
+ * Destroy the appropriate control structures corresponding
+ * the the EHCI host controller.
+ */
+int ehci_hcd_stop(void)
+{
+	return 0;
+}
diff --git a/drivers/usb/usb_ehci_fsl.h b/drivers/usb/usb_ehci_fsl.h
new file mode 100644
index 0000000..94e8650
--- /dev/null
+++ b/drivers/usb/usb_ehci_fsl.h
@@ -0,0 +1,82 @@
+/* Copyright (c) 2005 freescale semiconductor
+ * Copyright (c) 2005 MontaVista Software
+ * Copyright (c) 2008 Excito Elektronik i Sk=E5ne AB
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef _EHCI_FSL_H
+#define _EHCI_FSL_H
+/* Global offsets */
+#define FSL_SKIP_PCI 0x100
+
+/* offsets for the non-ehci registers in the FSL SOC USB controller */
+#define FSL_SOC_USB_ULPIVP	0x170
+#define FSL_SOC_USB_PORTSC1	0x184
+#define PORT_PTS_MSK		(3<<30)
+#define PORT_PTS_UTMI		(0<<30)
+#define PORT_PTS_ULPI		(2<<30)
+#define	PORT_PTS_SERIAL		(3<<30)
+#define PORT_PTS_PTW		(1<<28)
+
+/* USBMODE Register bits */
+#define CM_IDLE				(0<<0)
+#define CM_RESERVED			(1<<0)
+#define CM_DEVICE			(2<<0)
+#define CM_HOST				(3<<0)
+#define USBMODE_RESERVED_2	(0<<2)
+#define SLOM				(1<<3)
+#define SDIS				(1<<4)
+
+/* CONTROL Register bits */
+#define ULPI_INT_EN			(1<<0)
+#define WU_INT_EN			(1<<1)
+#define USB_EN				(1<<2)
+#define LSF_EN				(1<<3)
+#define KEEP_OTG_ON			(1<<4)
+#define OTG_PORT			(1<<5)
+#define REFSEL_12MHZ		(0<<6)
+#define REFSEL_16MHZ		(1<<6)
+#define REFSEL_48MHZ		(2<<6)
+#define PLL_RESET			(1<<8)
+#define UTMI_PHY_EN			(1<<9)
+#define PHY_CLK_SEL_UTMI	(0<<10)
+#define PHY_CLK_SEL_ULPI	(1<<10)
+#define CLKIN_SEL_USB_CLK	(0<<11)
+#define CLKIN_SEL_USB_CLK2	(1<<11)
+#define CLKIN_SEL_SYS_CLK	(2<<11)
+#define CLKIN_SEL_SYS_CLK2	(3<<11)
+#define RESERVED_18			(0<<13)
+#define RESERVED_17			(0<<14)
+#define RESERVED_16			(0<<15)
+#define WU_INT				(1<<16)
+#define PHY_CLK_VALID		(1<<17)
+
+#define FSL_SOC_USB_PORTSC2	0x188
+#define FSL_SOC_USB_USBMODE	0x1a8
+#define FSL_SOC_USB_SNOOP1	0x400	/* NOTE: big-endian */
+#define FSL_SOC_USB_SNOOP2	0x404	/* NOTE: big-endian */
+#define FSL_SOC_USB_AGECNTTHRSH	0x408	/* NOTE: big-endian */
+#define FSL_SOC_USB_PRICTRL	0x40c	/* NOTE: big-endian */
+#define FSL_SOC_USB_SICTRL	0x410	/* NOTE: big-endian */
+#define FSL_SOC_USB_CTRL	0x500	/* NOTE: big-endian */
+#define SNOOP_SIZE_2GB		0x1e
+
+/* System Clock Control Register */
+#define MPC83XX_SCCR_USB_MASK		0x00f00000
+#define MPC83XX_SCCR_USB_DRCM_11	0x00300000
+#define MPC83XX_SCCR_USB_DRCM_01	0x00100000
+#define MPC83XX_SCCR_USB_DRCM_10	0x00200000
+
+#endif /* _EHCI_FSL_H */
-- 
1.5.6.5



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