[U-Boot] [PATCH 0/6] DDR intereleaving support

[Haiying Wang]

Current new DDR code has included DDR interleaving support but has not
been tested out. The following patches fix the bugs for common code,
enable run time configuration of memory controller interleaving mode and
bank interleaving mode and add board specific parameters table to
decides the ddr controller options. The DDR interleaving support was
tested on MPC8572DS and MPC8641HPCN with some (not all) of the
interleaving modes.

On MPC8572DS board, I tested two kinds of memory modules:
* 2 X 512MB single-rank DDR2 DIMM
* 2 X 1GB single-rank DDR2 DIMM
at 1500/600/800(CPU/CCB/DDR)MHz frequency, by using "bw_mem", the memory
bandwith benchmark in LMbench. 

The following interleaving combination are tested: 
 +-------------+--------------------+
 |             |   Bank Interleaving|
 |             +--------+-----------+
 |Memory       |        |           |
 |Controller   |  None  | 2x1 lower |
 |Interleaving |        | {CS0+CS1} |
 +-------------+--------+-----------+
 |None         |  Yes   | Yes       |
 +-------------+--------+-----------+
 |Cacheline    |  Yes   | Yes       |
 |             |CS0 Only|           |
 +-------------+--------+-----------+
 |Page         |  Yes   | Yes       |
 |             |CS0 Only|           |
 +-------------+--------+-----------+
 |Bank         |  Yes   | Yes       |
 |             |CS0 Only|           |
 +-------------+--------+-----------+
 |Superbank    |  No    | Yes       |
 |             |        |           |
 +-------------+--------+-----------+

On MPC8641HPCN board, I tested three kinds of memory modules:
* 2 X 512MB single-rank DDR2 DIMM
* 4 X 512MB single-rank DDR2 DIMM
* 2 X 1GB single-rank DDR2 DIMM
I also tested CS2+CS3 interleaving mode on MPC8641HPCN board.

Haiying