[U-Boot] [PATCH 1/1 v2] ppc4xx: Reset and relock memory DLL after SDRAM_CLKTR change

[Stefan Roese]

Adam,

On Wednesday 08 October 2008, Stefan Roese wrote:
> On Monday 06 October 2008, Adam Graham wrote:
> > After changing SDRAM_CLKTR phase value rerun the memory preload
> > initialization sequence (INITPLR) to reset and relock the memory
> > DLL. Changing the SDRAM_CLKTR memory clock phase coarse timing
> > adjustment effects the phase relationship of the internal, to the
> > PPC chip, and external, to the PPC chip, versions of MEMCLK_OUT.
>
> Applied ppc4xx/master. Thanks.

Ups. I just gave this version another try on my 600MHz Kilauea board. And as 
it seems it definitely works better than without this patch, but it doesn't 
work reliably. :-(

Here some outputs after rebooting:


U-Boot 2008.10-rc2-02708-gf8a00de (Oct  8 2008 - 11:40:49)

CPU:   AMCC PowerPC 405EX Rev. C at 600 MHz (PLB=200, OPB=100, EBC=100 MHz)
       Security support
       Bootstrap Option H - Boot ROM Location I2C (Addr 0x52)
       16 kB I-Cache 16 kB D-Cache
Board: Kilauea - AMCC PPC405EX Evaluation Board
I2C:   ready
DTT1:  FAILED
DRAM:  256 MB


U-Boot 2008.10-rc2-02708-gf8a00de (Oct  8 2008 - 11:40:49)

CPU:   AMCC PowerPC 405EX Rev. C at 600 MHz (PLB=200, OPB=100, EBC=100 MHz)
       Security support
       Bootstrap Option H - Boot ROM Location I2C (Addr 0x52)
       16 kB I-Cache 16 kB D-Cache
Board: Kilauea - AMCC PPC405EX Evaluation Board
I2C:   ready
DTT1:  FAILED
DRAM:  256 MB
Memory error at 01cff924, wrote 00000200, read aaaa0200 !


This didn't happen with the temporary patch you sent out a few weeks ago. This 
error occurs often after pushing the reset button on the Kilauea. I suggest 
that you take another look at this issue on your 600MHz board. Perhaps make a 
long test by setting "bootcmd" to "reset". If the board still resets after 
running for some hours, then you should be safe.

BTW: I won't ask Wolfgang to pull for now. 

Thanks.

Best regards,
Stefan

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