[U-Boot] [PATCH] mpc83xx: add ELBC NAND support for the MPC837XEMDSboards
Liu Dave-R63238
DaveLiu at freescale.com
Thu Oct 9 06:26:34 CEST 2008
It is due to hardware design and logic defect, that is the
I/O[0:7] of NAND chip is connected to LAD[7:0], so when
the NAND chip connected to nLCS3, you have to set up the
OR3[BCTLD] = '1' for normal operation, otherwise it will have
bus contention due to the pin 48/25 of U60 is enabled.
Setup the OR3[BCTLD] = '1' , that meaning the LBCTL is not
asserted upon access to the NAND chip, keep the default state.
Acked-by: Dave Liu <daveliu at freescale.com>
> -----Original Message-----
> From: u-boot-bounces at lists.denx.de
> [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Anton Vorontsov
> Sent: 2008?10?9? 12:53 AM
> To: Phillips Kim-R1AAHA
> Cc: u-boot at lists.denx.de
> Subject: [U-Boot] [PATCH] mpc83xx: add ELBC NAND support for
> the MPC837XEMDSboards
>
> Though NAND chip is replaceable on the MPC837XE-MDS boards, the
> current settings don't work with the default chip on the board.
> Nevertheless Freescale's U-Boot sets the option register correctly,
> so I just dumped the register from the working u-boot. My guess is
> that the old settings were applicable for some pilot boards, not
> found in the production.
>
> This patch also enables FSL ELBC driver so that we could access
> the NAND storage in the u-boot.
>
> The NAND support costs about 45KB, so the u-boot no longer fits
> into two 128KB NOR flash sectors, thus we also have to adjust
> environment location: add another 128KB to the monitor length.
>
> Signed-off-by: Anton Vorontsov <avorontsov at ru.mvista.com>
> ---
> include/configs/MPC837XEMDS.h | 13 ++++++++++---
> 1 files changed, 10 insertions(+), 3 deletions(-)
>
> diff --git a/include/configs/MPC837XEMDS.h
> b/include/configs/MPC837XEMDS.h
> index adf7c8c..d78aa60 100644
> --- a/include/configs/MPC837XEMDS.h
> +++ b/include/configs/MPC837XEMDS.h
> @@ -204,7 +204,7 @@
> #endif
>
> /* CFG_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
> -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve
> 256 kB for Mon */
> +#define CFG_MONITOR_LEN (384 * 1024) /* Reserve
> 384 kB for Mon */
> #define CFG_MALLOC_LEN (512 * 1024) /*
> Reserved for malloc */
>
> /*
> @@ -267,6 +267,12 @@
> /*
> * NAND Flash on the Local Bus
> */
> +#define CONFIG_CMD_NAND 1
> +#define CONFIG_MTD_NAND_VERIFY_WRITE 1
> +#define CFG_MAX_NAND_DEVICE 1
> +#define NAND_MAX_CHIPS 1
> +#define CONFIG_NAND_FSL_ELBC 1
> +
> #define CFG_NAND_BASE 0xE0600000 /* 0xE0600000 */
> #define CFG_BR3_PRELIM ( CFG_NAND_BASE \
> | (2<<BR_DECC_SHIFT) /* Use
> HW ECC */ \
> @@ -274,13 +280,14 @@
> | BR_MS_FCM /* MSEL
> = FCM */ \
> | BR_V ) /* valid */
> #define CFG_OR3_PRELIM ( 0xFFFF8000
> /* length 32K */ \
> - | OR_FCM_CSCT \
> + | OR_FCM_BCTLD \
> | OR_FCM_CST \
> | OR_FCM_CHT \
> | OR_FCM_SCY_1 \
> + | OR_FCM_RST \
> | OR_FCM_TRLX \
> | OR_FCM_EHTR )
> - /* 0xFFFF8396 */
> + /* 0xFFFF919E */
>
> #define CFG_LBLAWBAR3_PRELIM CFG_NAND_BASE
> #define CFG_LBLAWAR3_PRELIM 0x8000000E /* 32KB */
> --
> 1.5.6.3
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